[PATCH] D70771: [PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules
qshanz via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 16 18:53:48 PST 2020
steven.zhang updated this revision to Diff 244909.
steven.zhang added a comment.
Seems that the pre merge checker has problem in detecting the dependent patch landing or not. Remove the parent revision and trigger the check again.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70771/new/
https://reviews.llvm.org/D70771
Files:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
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