[PATCH] D74360: [llvm][TableGen] Define FieldInit::isConcrete overload

[River Riddle via Phabricator via llvm-commits]

rriddle added a comment.

In D74360#1878327 <https://reviews.llvm.org/D74360#1878327>, @nhaehnle wrote:

> Do you have a concrete example where this is used? I would have expected the A1.value to be resolved... the non-resolve-behavior was only kept around for bits in instruction encodings (Resolver::keepUnsetBits).


This happens in MLIR where we use tablegen quite a bit, e.g. for defining operations.

https://github.com/llvm/llvm-project/blob/272d35aef5e0d32f12b700ea12c608e0323ceb3f/mlir/include/mlir/IR/OpBase.td#L683
https://github.com/llvm/llvm-project/blob/272d35aef5e0d32f12b700ea12c608e0323ceb3f/mlir/include/mlir/IR/OpBase.td#L636


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