[llvm] 922197d - [TBLGEN] Allow to override RC weight
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 14 15:50:03 PST 2020
Author: Stanislav Mekhanoshin
Date: 2020-02-14T15:49:52-08:00
New Revision: 922197d664d34612e0bd657b066a0bf0d392e774
URL: https://github.com/llvm/llvm-project/commit/922197d664d34612e0bd657b066a0bf0d392e774
DIFF: https://github.com/llvm/llvm-project/commit/922197d664d34612e0bd657b066a0bf0d392e774.diff
LOG: [TBLGEN] Allow to override RC weight
Differential Revision: https://reviews.llvm.org/D74509
Added:
llvm/test/TableGen/rc-weight-override.td
Modified:
llvm/include/llvm/Target/Target.td
llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
llvm/lib/Target/AMDGPU/R600RegisterInfo.h
llvm/lib/Target/AMDGPU/R600RegisterInfo.td
llvm/utils/TableGen/CodeGenRegisters.cpp
llvm/utils/TableGen/CodeGenRegisters.h
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index eda08bb28d4c..38abbcebfdf5 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -276,6 +276,13 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// constrained classes first. The value has to be in the range [0,63].
int AllocationPriority = 0;
+ // Weight override for register pressure calculation. This is the value
+ // TargetRegisterClass::getRegClassWeight() will return. The weight is in
+ // units of pressure for this register class. If unset tablegen will
+ // calculate a weight based on a number of register units in this register
+ // class registers. The weight is per register.
+ int Weight = ?;
+
// The diagnostic type to present when referencing this operand in a match
// failure error message. If this is empty, the default Match_InvalidOperand
// diagnostic type will be used. If this is "<name>", a Match_<name> enum
diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
index 29b038a04cfc..78ef71cdf8e3 100644
--- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
@@ -20,11 +20,6 @@
using namespace llvm;
-R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
- RCW.RegWeight = 0;
- RCW.WeightLimit = 0;
-}
-
#define GET_REGINFO_TARGET_DESC
#include "R600GenRegisterInfo.inc"
@@ -99,11 +94,6 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
}
}
-const RegClassWeight &R600RegisterInfo::getRegClassWeight(
- const TargetRegisterClass *RC) const {
- return RCW;
-}
-
bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
assert(!Register::isVirtualRegister(Reg));
diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.h b/llvm/lib/Target/AMDGPU/R600RegisterInfo.h
index 771d7d33fd2e..06981c4cf9c5 100644
--- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.h
@@ -20,9 +20,7 @@
namespace llvm {
struct R600RegisterInfo final : public R600GenRegisterInfo {
- RegClassWeight RCW;
-
- R600RegisterInfo();
+ R600RegisterInfo() : R600GenRegisterInfo(0) {}
/// \returns the sub reg enum value for the given \p Channel
/// (e.g. getSubRegFromChannel(0) -> R600::sub0)
@@ -41,9 +39,6 @@ struct R600RegisterInfo final : public R600GenRegisterInfo {
/// CFGStructurizer
const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
- const RegClassWeight &
- getRegClassWeight(const TargetRegisterClass *RC) const override;
-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.td b/llvm/lib/Target/AMDGPU/R600RegisterInfo.td
index 02164b74a01b..fdff7541edec 100644
--- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.td
@@ -150,13 +150,16 @@ def AR_X : R600Reg<"AR.x", 0>;
def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;
def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
- (add (sequence "ArrayBase%u", 448, 480))>;
+ (add (sequence "ArrayBase%u", 448, 480))> {
+ let Weight = 0;
+}
// special registers for ALU src operands
// const buffer reference, SRCx_SEL contains index
def ALU_CONST : R600Reg<"CBuf", 0>;
// interpolation param reference, SRCx_SEL contains index
def ALU_PARAM : R600Reg<"Param", 0>;
+let Weight = 0 in {
let isAllocatable = 0 in {
def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
@@ -251,3 +254,4 @@ def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,
def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
(add V01_X, V01_Y, V01_Z, V01_W,
V23_X, V23_Y, V23_Z, V23_W)>;
+} // End let Weight = 0
diff --git a/llvm/test/TableGen/rc-weight-override.td b/llvm/test/TableGen/rc-weight-override.td
new file mode 100644
index 000000000000..0a71192ff8bd
--- /dev/null
+++ b/llvm/test/TableGen/rc-weight-override.td
@@ -0,0 +1,24 @@
+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+
+include "reg-with-subregs-common.td"
+
+// CHECK-LABEL: static const RegClassWeight RCWeightTable[] = {
+// CHECK: {1, 256}, // GPR32
+// CHECK: {2, 256}, // GPR_64
+
+// CHECK: {0, 256}, // GPR_64_W0
+def GPR_64_W0 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
+ let Weight = 0;
+}
+
+// CHECK: {1, 256}, // GPR_64_W1
+def GPR_64_W1 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
+ let Weight = 1;
+}
+
+// CHECK: {8, 256}, // GPR_64_W8
+def GPR_64_W8 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
+ let Weight = 8;
+}
+
+// CHECK: {32, 256}, // GPR_1024
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index dd70e2ff6896..5e88bf8553af 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -854,6 +854,16 @@ bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
deref<std::less<>>());
}
+unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank& RegBank) const {
+ if (TheDef && !TheDef->isValueUnset("Weight"))
+ return TheDef->getValueAsInt("Weight");
+
+ if (Members.empty() || Artificial)
+ return 0;
+
+ return (*Members.begin())->getWeight(RegBank);
+}
+
namespace llvm {
raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index 8d790321a002..510279ddfeb4 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -438,6 +438,9 @@ namespace llvm {
// Get a bit vector of TopoSigs present in this register class.
const BitVector &getTopoSigs() const { return TopoSigs; }
+ // Get a weight of this register class.
+ unsigned getWeight(const CodeGenRegBank&) const;
+
// Populate a unique sorted list of units from a register set.
void buildRegUnitSet(const CodeGenRegBank &RegBank,
std::vector<unsigned> &RegUnits) const;
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 472a3de47816..f9766931344d 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -202,13 +202,13 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
<< " static const RegClassWeight RCWeightTable[] = {\n";
for (const auto &RC : RegBank.getRegClasses()) {
const CodeGenRegister::Vec &Regs = RC.getMembers();
+ OS << " {" << RC.getWeight(RegBank) << ", ";
if (Regs.empty() || RC.Artificial)
- OS << " {0, 0";
+ OS << '0';
else {
std::vector<unsigned> RegUnits;
RC.buildRegUnitSet(RegBank, RegUnits);
- OS << " {" << (*Regs.begin())->getWeight(RegBank)
- << ", " << RegBank.getRegUnitSetWeight(RegUnits);
+ OS << RegBank.getRegUnitSetWeight(RegUnits);
}
OS << "}, \t// " << RC.getName() << "\n";
}
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