[PATCH] D74338: [RFC][TableGen/RISCV] Support combining AssemblerPredicates with ORs

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added a comment.

We have a similar situation in the ARM backend, where there are a few move/load/store instructions operating on FP regs, which are available with either FeatureVFPv2_SP or HasIntegerMVEOps. We solved this by adding new target features for these common instructions, and adding dependencies from the other features to them, so that they get enabled whenever the "real" features are enabled. This works, but has the downside that clang now needs to disable these features when disabling the VFP/MVE features. This patch looks like a better solution to the problem, since clang doesn't need to know about the shared instructions.


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https://reviews.llvm.org/D74338