[llvm] b23ec43 - [AArch64][NFC] Update test checks.
Pavel Iliin via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 13 16:16:25 PST 2020
Author: Pavel Iliin
Date: 2020-02-14T00:13:15Z
New Revision: b23ec439738a0480eaf57a22ee52f136babaaa66
URL: https://github.com/llvm/llvm-project/commit/b23ec439738a0480eaf57a22ee52f136babaaa66
DIFF: https://github.com/llvm/llvm-project/commit/b23ec439738a0480eaf57a22ee52f136babaaa66.diff
LOG: [AArch64][NFC] Update test checks.
This NFC commit updates several llc tests checks by automatically generated ones.
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
index fe765f4ef984..464726b0d2f3 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
@@ -1,13 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \
-; RUN: < %s -verify-machineinstrs -asm-verbose=false | FileCheck %s
+; RUN: < %s -verify-machineinstrs | FileCheck %s
define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {
; CHECK-LABEL: test_select_cc_v8i8_i8:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b
-; CHECK: dup [[DUPMASK:v[0-9]+]].8b, [[MASK]].b[0]
-; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.8b, v3.8b, v2.8b
+; CHECK-NEXT: dup v2.8b, v2.b[0]
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i8 %a, %b
%e = select i1 %cmp31, <8x i8> %c, <8x i8> %d
ret <8x i8> %e
@@ -15,9 +19,13 @@ define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {
define <8x i8> @test_select_cc_v8i8_f32(float %a, float %b, <8x i8> %c, <8x i8> %d ) {
; CHECK-LABEL: test_select_cc_v8i8_f32:
-; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
-; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
-; CHECK-NEXT: bsl [[DUPMASK]].8b, v2.8b, v3.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $d1
+; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq float %a, %b
%e = select i1 %cmp31, <8x i8> %c, <8x i8> %d
ret <8x i8> %e
@@ -25,8 +33,10 @@ define <8x i8> @test_select_cc_v8i8_f32(float %a, float %b, <8x i8> %c, <8x i8>
define <8x i8> @test_select_cc_v8i8_f64(double %a, double %b, <8x i8> %c, <8x i8> %d ) {
; CHECK-LABEL: test_select_cc_v8i8_f64:
-; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
-; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmeq d0, d0, d1
+; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq double %a, %b
%e = select i1 %cmp31, <8x i8> %c, <8x i8> %d
ret <8x i8> %e
@@ -34,11 +44,14 @@ define <8x i8> @test_select_cc_v8i8_f64(double %a, double %b, <8x i8> %c, <8x i8
define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d ) {
; CHECK-LABEL: test_select_cc_v16i8_i8:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b
-; CHECK: dup [[DUPMASK:v[0-9]+]].16b, [[MASK]].b[0]
-; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.16b, v3.16b, v2.16b
+; CHECK-NEXT: dup v2.16b, v2.b[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i8 %a, %b
%e = select i1 %cmp31, <16x i8> %c, <16x i8> %d
ret <16x i8> %e
@@ -46,9 +59,13 @@ define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d
define <16x i8> @test_select_cc_v16i8_f32(float %a, float %b, <16x i8> %c, <16x i8> %d ) {
; CHECK-LABEL: test_select_cc_v16i8_f32:
-; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
-; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
-; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v0.4s, v0.s[0]
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq float %a, %b
%e = select i1 %cmp31, <16x i8> %c, <16x i8> %d
ret <16x i8> %e
@@ -56,9 +73,13 @@ define <16x i8> @test_select_cc_v16i8_f32(float %a, float %b, <16x i8> %c, <16x
define <16x i8> @test_select_cc_v16i8_f64(double %a, double %b, <16x i8> %c, <16x i8> %d ) {
; CHECK-LABEL: test_select_cc_v16i8_f64:
-; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
-; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
-; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v0.2d, v0.d[0]
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq double %a, %b
%e = select i1 %cmp31, <16x i8> %c, <16x i8> %d
ret <16x i8> %e
@@ -66,11 +87,14 @@ define <16x i8> @test_select_cc_v16i8_f64(double %a, double %b, <16x i8> %c, <16
define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d ) {
; CHECK-LABEL: test_select_cc_v4i16:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].4h, v[[LHS]].4h, v[[RHS]].4h
-; CHECK: dup [[DUPMASK:v[0-9]+]].4h, [[MASK]].h[0]
-; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.4h, v3.4h, v2.4h
+; CHECK-NEXT: dup v2.4h, v2.h[0]
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i16 %a, %b
%e = select i1 %cmp31, <4x i16> %c, <4x i16> %d
ret <4x i16> %e
@@ -78,11 +102,14 @@ define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d )
define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d ) {
; CHECK-LABEL: test_select_cc_v8i16:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].8h, v[[LHS]].8h, v[[RHS]].8h
-; CHECK: dup [[DUPMASK:v[0-9]+]].8h, [[MASK]].h[0]
-; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.8h, v3.8h, v2.8h
+; CHECK-NEXT: dup v2.8h, v2.h[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i16 %a, %b
%e = select i1 %cmp31, <8x i16> %c, <8x i16> %d
ret <8x i16> %e
@@ -90,11 +117,14 @@ define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d )
define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) {
; CHECK-LABEL: test_select_cc_v2i32:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].2s, v[[LHS]].2s, v[[RHS]].2s
-; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
-; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.2s, v3.2s, v2.2s
+; CHECK-NEXT: dup v2.2s, v2.s[0]
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i32 %a, %b
%e = select i1 %cmp31, <2x i32> %c, <2x i32> %d
ret <2x i32> %e
@@ -102,11 +132,14 @@ define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d )
define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) {
; CHECK-LABEL: test_select_cc_v4i32:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s
-; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
-; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.4s, v3.4s, v2.4s
+; CHECK-NEXT: dup v2.4s, v2.s[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i32 %a, %b
%e = select i1 %cmp31, <4x i32> %c, <4x i32> %d
ret <4x i32> %e
@@ -114,10 +147,13 @@ define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d )
define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) {
; CHECK-LABEL: test_select_cc_v1i64:
-; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0
-; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1
-; CHECK: cmeq d[[MASK:[0-9]+]], d[[LHS]], d[[RHS]]
-; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d2, x1
+; CHECK-NEXT: fmov d3, x0
+; CHECK-NEXT: cmeq d2, d3, d2
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i64 %a, %b
%e = select i1 %cmp31, <1x i64> %c, <1x i64> %d
ret <1x i64> %e
@@ -125,11 +161,14 @@ define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d )
define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) {
; CHECK-LABEL: test_select_cc_v2i64:
-; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0
-; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1
-; CHECK: cmeq [[MASK:v[0-9]+]].2d, v[[LHS]].2d, v[[RHS]].2d
-; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
-; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d2, x1
+; CHECK-NEXT: fmov d3, x0
+; CHECK-NEXT: cmeq v2.2d, v3.2d, v2.2d
+; CHECK-NEXT: dup v2.2d, v2.d[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i64 %a, %b
%e = select i1 %cmp31, <2x i64> %c, <2x i64> %d
ret <2x i64> %e
@@ -137,8 +176,12 @@ define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d )
define <1 x float> @test_select_cc_v1f32(float %a, float %b, <1 x float> %c, <1 x float> %d ) {
; CHECK-LABEL: test_select_cc_v1f32:
-; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
-; CHECK-NEXT: bsl [[MASK]].8b, v2.8b, v3.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $d1
+; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq float %a, %b
%e = select i1 %cmp31, <1 x float> %c, <1 x float> %d
ret <1 x float> %e
@@ -146,9 +189,13 @@ define <1 x float> @test_select_cc_v1f32(float %a, float %b, <1 x float> %c, <1
define <2 x float> @test_select_cc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d ) {
; CHECK-LABEL: test_select_cc_v2f32:
-; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
-; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
-; CHECK: bsl [[DUPMASK]].8b, v2.8b, v3.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $d1
+; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v0.2s, v0.s[0]
+; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq float %a, %b
%e = select i1 %cmp31, <2 x float> %c, <2 x float> %d
ret <2 x float> %e
@@ -156,9 +203,13 @@ define <2 x float> @test_select_cc_v2f32(float %a, float %b, <2 x float> %c, <2
define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x float> %d ) {
; CHECK-LABEL: test_select_cc_v4f32:
-; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
-; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
-; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v0.4s, v0.s[0]
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq float %a, %b
%e = select i1 %cmp31, <4x float> %c, <4x float> %d
ret <4x float> %e
@@ -166,11 +217,14 @@ define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x f
define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x float> %d ) {
; CHECK-LABEL: test_select_cc_v4f32_icmp:
-; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
-; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
-; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s
-; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
-; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s2, w1
+; CHECK-NEXT: fmov s3, w0
+; CHECK-NEXT: cmeq v2.4s, v3.4s, v2.4s
+; CHECK-NEXT: dup v2.4s, v2.s[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i32 %a, %b
%e = select i1 %cmp31, <4x float> %c, <4x float> %d
ret <4x float> %e
@@ -178,8 +232,10 @@ define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x
define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c, <1 x double> %d ) {
; CHECK-LABEL: test_select_cc_v1f64:
-; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
-; CHECK: bsl v[[MASK]].8b, v2.8b, v3.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmeq d0, d0, d1
+; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq double %a, %b
%e = select i1 %cmp31, <1 x double> %c, <1 x double> %d
ret <1 x double> %e
@@ -187,10 +243,13 @@ define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c,
define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, <1 x double> %d ) {
; CHECK-LABEL: test_select_cc_v1f64_icmp:
-; CHECK-DAG: fmov [[LHS:d[0-9]+]], x0
-; CHECK-DAG: fmov [[RHS:d[0-9]+]], x1
-; CHECK: cmeq d[[MASK:[0-9]+]], [[LHS]], [[RHS]]
-; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d2, x1
+; CHECK-NEXT: fmov d3, x0
+; CHECK-NEXT: cmeq d2, d3, d2
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp31 = icmp eq i64 %a, %b
%e = select i1 %cmp31, <1 x double> %c, <1 x double> %d
ret <1 x double> %e
@@ -198,9 +257,13 @@ define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c,
define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d ) {
; CHECK-LABEL: test_select_cc_v2f64:
-; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
-; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
-; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v0.2d, v0.d[0]
+; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
+; CHECK-NEXT: ret
%cmp31 = fcmp oeq double %a, %b
%e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
ret <2 x double> %e
@@ -211,11 +274,13 @@ define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c,
; Part of PR21549.
define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: test_select_cc_v2i32_icmpi1:
-; CHECK: tst w0, #0x1
-; CHECK: csetm [[MASK:w[0-9]+]], ne
-; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]]
-; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
-; CHECK: mov v0.16b, [[DUPMASK]].16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: tst w0, #0x1
+; CHECK-NEXT: csetm w8, ne
+; CHECK-NEXT: dup v2.2s, w8
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cmp = icmp ne i1 %cc, 0
%e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %e
@@ -224,11 +289,14 @@ define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b
; Also make sure we support irregular/non-power-of-2 types such as v3f32.
define <3 x float> @test_select_cc_v3f32_fcmp_f32(<3 x float> %a, <3 x float> %b, float %c1, float %c2) #0 {
; CHECK-LABEL: test_select_cc_v3f32_fcmp_f32:
-; CHECK-NEXT: fcmeq [[MASK:v[0-9]+]].4s, v2.4s, v3.4s
-; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
-; CHECK-NEXT: bsl [[DUPMASK:v[0-9]+]].16b, v0.16b, v1.16b
-; CHECK-NEXT: mov v0.16b, [[DUPMASK]].16b
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: fcmeq v2.4s, v2.4s, v3.4s
+; CHECK-NEXT: dup v2.4s, v2.s[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cc = fcmp oeq float %c1, %c2
%r = select i1 %cc, <3 x float> %a, <3 x float> %b
ret <3 x float> %r
@@ -236,11 +304,14 @@ define <3 x float> @test_select_cc_v3f32_fcmp_f32(<3 x float> %a, <3 x float> %b
define <3 x float> @test_select_cc_v3f32_fcmp_f64(<3 x float> %a, <3 x float> %b, double %c1, double %c2) #0 {
; CHECK-LABEL: test_select_cc_v3f32_fcmp_f64:
-; CHECK-NEXT: fcmeq [[MASK:v[0-9]+]].2d, v2.2d, v3.2d
-; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
-; CHECK-NEXT: bsl [[DUPMASK:v[0-9]+]].16b, v0.16b, v1.16b
-; CHECK-NEXT: mov v0.16b, [[DUPMASK]].16b
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: fcmeq v2.2d, v2.2d, v3.2d
+; CHECK-NEXT: dup v2.2d, v2.d[0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%cc = fcmp oeq double %c1, %c2
%r = select i1 %cc, <3 x float> %a, <3 x float> %b
ret <3 x float> %r
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
index 1f67ff4e938a..59afe47042ff 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
@@ -1,9 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
; float16x4_t select_64(float16x4_t a, float16x4_t b, uint16x4_t c) { return vbsl_u16(c, a, b); }
define <4 x half> @select_64(<4 x half> %a, <4 x half> %b, <4 x i16> %c) #0 {
; CHECK-LABEL: select_64:
-; CHECK: bsl
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
entry:
%0 = bitcast <4 x half> %a to <4 x i16>
%1 = bitcast <4 x half> %b to <4 x i16>
@@ -18,7 +22,10 @@ entry:
; float16x8_t select_128(float16x8_t a, float16x8_t b, uint16x8_t c) { return vbslq_u16(c, a, b); }
define <8 x half> @select_128(<8 x half> %a, <8 x half> %b, <8 x i16> %c) #0 {
; CHECK-LABEL: select_128:
-; CHECK: bsl
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%1 = bitcast <8 x half> %b to <8 x i16>
@@ -35,7 +42,12 @@ entry:
; }
define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-LABEL: lane_64_64:
-; CHECK: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.h[1], v1.h[2]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
ret <4 x half> %0
@@ -46,7 +58,10 @@ entry:
; }
define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 {
; CHECK-LABEL: lane_128_64:
-; CHECK: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.h[1], v1.h[2]
+; CHECK-NEXT: ret
entry:
%0 = bitcast <4 x half> %b to <4 x i16>
%vget_lane = extractelement <4 x i16> %0, i32 2
@@ -61,7 +76,11 @@ entry:
; }
define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 {
; CHECK-LABEL: lane_64_128:
-; CHECK: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.h[3], v1.h[5]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%0 = bitcast <8 x half> %b to <8 x i16>
%vgetq_lane = extractelement <8 x i16> %0, i32 5
@@ -76,7 +95,9 @@ entry:
; }
define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-LABEL: lane_128_128:
-; CHECK: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov v0.h[3], v1.h[5]
+; CHECK-NEXT: ret
entry:
%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %0
@@ -87,7 +108,9 @@ entry:
; }
define <4 x half> @ext_64(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-LABEL: ext_64:
-; CHECK: ext
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6
+; CHECK-NEXT: ret
entry:
%0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
ret <4 x half> %0
@@ -98,7 +121,9 @@ entry:
; }
define <8 x half> @ext_128(<8 x half> %a, <8 x half> %b) #0 {
; CHECK-LABEL: ext_128:
-; CHECK: ext
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #6
+; CHECK-NEXT: ret
entry:
%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <8 x half> %0
@@ -108,9 +133,11 @@ entry:
; return vrev32_s16(a);
; }
define <4 x half> @rev32_64(<4 x half> %a) #0 {
-entry:
; CHECK-LABEL: rev32_64:
-; CHECK: rev32
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v0.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
%0 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x half> %0
}
@@ -119,9 +146,11 @@ entry:
; return vrev64_s16(a);
; }
define <4 x half> @rev64_64(<4 x half> %a) #0 {
-entry:
; CHECK-LABEL: rev64_64:
-; CHECK: rev64
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
%0 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x half> %0
}
@@ -130,9 +159,11 @@ entry:
; return vrev32q_s16(a);
; }
define <8 x half> @rev32_128(<8 x half> %a) #0 {
-entry:
; CHECK-LABEL: rev32_128:
-; CHECK: rev32
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 v0.8h, v0.8h
+; CHECK-NEXT: ret
+entry:
%0 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x half> %0
}
@@ -141,9 +172,11 @@ entry:
; return vrev64q_s16(a);
; }
define <8 x half> @rev64_128(<8 x half> %a) #0 {
-entry:
; CHECK-LABEL: rev64_128:
-; CHECK: rev64
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ret
+entry:
%0 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x half> %0
}
@@ -151,7 +184,9 @@ entry:
; float16x4_t create_64(long long a) { return vcreate_f16(a); }
define <4 x half> @create_64(i64 %a) #0 {
; CHECK-LABEL: create_64:
-; CHECK: fmov
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fmov d0, x0
+; CHECK-NEXT: ret
entry:
%0 = bitcast i64 %a to <4 x half>
ret <4 x half> %0
@@ -160,7 +195,10 @@ entry:
; float16x4_t dup_64(__fp16 a) { return vdup_n_f16(a); }
define <4 x half> @dup_64(half %a) #0 {
; CHECK-LABEL: dup_64:
-; CHECK: dup
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
+; CHECK-NEXT: dup v0.4h, v0.h[0]
+; CHECK-NEXT: ret
entry:
%vecinit = insertelement <4 x half> undef, half %a, i32 0
%vecinit1 = insertelement <4 x half> %vecinit, half %a, i32 1
@@ -171,9 +209,12 @@ entry:
; float16x8_t dup_128(__fp16 a) { return vdupq_n_f16(a); }
define <8 x half> @dup_128(half %a) #0 {
-entry:
; CHECK-LABEL: dup_128:
-; CHECK: dup
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
+; CHECK-NEXT: dup v0.8h, v0.h[0]
+; CHECK-NEXT: ret
+entry:
%vecinit = insertelement <8 x half> undef, half %a, i32 0
%vecinit1 = insertelement <8 x half> %vecinit, half %a, i32 1
%vecinit2 = insertelement <8 x half> %vecinit1, half %a, i32 2
@@ -187,45 +228,59 @@ entry:
; float16x4_t dup_lane_64(float16x4_t a) { return vdup_lane_f16(a, 2); }
define <4 x half> @dup_lane_64(<4 x half> %a) #0 {
-entry:
; CHECK-LABEL: dup_lane_64:
-; CHECK: dup
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4h, v0.h[2]
+; CHECK-NEXT: ret
+entry:
%shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
ret <4 x half> %shuffle
}
; float16x8_t dup_lane_128(float16x4_t a) { return vdupq_lane_f16(a, 2); }
define <8 x half> @dup_lane_128(<4 x half> %a) #0 {
-entry:
; CHECK-LABEL: dup_lane_128:
-; CHECK: dup
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.8h, v0.h[2]
+; CHECK-NEXT: ret
+entry:
%shuffle = shufflevector <4 x half> %a, <4 x half> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
ret <8 x half> %shuffle
}
; float16x4_t dup_laneq_64(float16x8_t a) { return vdup_laneq_f16(a, 2); }
define <4 x half> @dup_laneq_64(<8 x half> %a) #0 {
-entry:
; CHECK-LABEL: dup_laneq_64:
-; CHECK: dup
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.4h, v0.h[2]
+; CHECK-NEXT: ret
+entry:
%shuffle = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
ret <4 x half> %shuffle
}
; float16x8_t dup_laneq_128(float16x8_t a) { return vdupq_laneq_f16(a, 2); }
define <8 x half> @dup_laneq_128(<8 x half> %a) #0 {
-entry:
; CHECK-LABEL: dup_laneq_128:
-; CHECK: dup
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.8h, v0.h[2]
+; CHECK-NEXT: ret
+entry:
%shuffle = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
ret <8 x half> %shuffle
}
; float16x8_t vcombine(float16x4_t a, float16x4_t b) { return vcombine_f16(a, b); }
define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {
-entry:
; CHECK-LABEL: vcombine:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
+entry:
%shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %shuffle.i
}
@@ -233,7 +288,10 @@ entry:
; float16x4_t get_high(float16x8_t a) { return vget_high_f16(a); }
define <4 x half> @get_high(<8 x half> %a) #0 {
; CHECK-LABEL: get_high:
-; CHECK: ext
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
ret <4 x half> %shuffle.i
@@ -243,7 +301,9 @@ entry:
; float16x4_t get_low(float16x8_t a) { return vget_low_f16(a); }
define <4 x half> @get_low(<8 x half> %a) #0 {
; CHECK-LABEL: get_low:
-; CHECK-NOT: ext
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %shuffle.i
@@ -252,8 +312,13 @@ entry:
; float16x4_t set_lane_64(float16x4_t a, __fp16 b) { return vset_lane_f16(b, a, 2); }
define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 {
; CHECK-LABEL: set_lane_64:
-; CHECK: fmov
-; CHECK: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.h[2], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%0 = bitcast half %b to i16
%1 = bitcast <4 x half> %a to <4 x i16>
@@ -266,8 +331,11 @@ entry:
; float16x8_t set_lane_128(float16x8_t a, __fp16 b) { return vsetq_lane_f16(b, a, 2); }
define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 {
; CHECK-LABEL: set_lane_128:
-; CHECK: fmov
-; CHECK: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1
+; CHECK-NEXT: fmov w8, s1
+; CHECK-NEXT: mov v0.h[2], w8
+; CHECK-NEXT: ret
entry:
%0 = bitcast half %b to i16
%1 = bitcast <8 x half> %a to <8 x i16>
@@ -279,8 +347,12 @@ entry:
; __fp16 get_lane_64(float16x4_t a) { return vget_lane_f16(a, 2); }
define half @get_lane_64(<4 x half> %a) #0 {
; CHECK-LABEL: get_lane_64:
-; CHECK: umov
-; CHECK: fmov
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: umov w8, v0.h[2]
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: ret
entry:
%0 = bitcast <4 x half> %a to <4 x i16>
%vget_lane = extractelement <4 x i16> %0, i32 2
@@ -291,8 +363,11 @@ entry:
; __fp16 get_lane_128(float16x8_t a) { return vgetq_lane_f16(a, 2); }
define half @get_lane_128(<8 x half> %a) #0 {
; CHECK-LABEL: get_lane_128:
-; CHECK: umov
-; CHECK: fmov
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: umov w8, v0.h[2]
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: ret
entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%vgetq_lane = extractelement <8 x i16> %0, i32 2
diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index 8af8fd2be94b..4fe52e7cae24 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -1,15 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: and8xi8:
-; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, %b;
ret <8 x i8> %tmp1
}
define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: and16xi8:
-; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, %b;
ret <16 x i8> %tmp1
}
@@ -17,14 +22,18 @@ define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: orr8xi8:
-; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, %b;
ret <8 x i8> %tmp1
}
define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: orr16xi8:
-; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, %b;
ret <16 x i8> %tmp1
}
@@ -32,22 +41,29 @@ define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: xor8xi8:
-; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <8 x i8> %a, %b;
ret <8 x i8> %tmp1
}
define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: xor16xi8:
-; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <16 x i8> %a, %b;
ret <16 x i8> %tmp1
}
define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: bsl8xi8_const:
-; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff0000ffff
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
%tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
%tmp3 = or <8 x i8> %tmp1, %tmp2
@@ -56,8 +72,11 @@ define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: bsl16xi8_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
%tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp3 = or <16 x i8> %tmp1, %tmp2
@@ -66,7 +85,9 @@ define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: orn8xi8:
-; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = or <8 x i8> %a, %tmp1
ret <8 x i8> %tmp2
@@ -74,7 +95,9 @@ define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: orn16xi8:
-; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = or <16 x i8> %a, %tmp1
ret <16 x i8> %tmp2
@@ -82,7 +105,9 @@ define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: bic8xi8:
-; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <8 x i8> %a, %tmp1
ret <8 x i8> %tmp2
@@ -90,7 +115,9 @@ define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: bic16xi8:
-; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <16 x i8> %a, %tmp1
ret <16 x i8> %tmp2
@@ -98,175 +125,225 @@ define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
; CHECK-LABEL: orrimm2s_lsl0:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, < i32 255, i32 255>
ret <2 x i32> %tmp1
}
define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
; CHECK-LABEL: orrimm2s_lsl8:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
ret <2 x i32> %tmp1
}
define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
; CHECK-LABEL: orrimm2s_lsl16:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
ret <2 x i32> %tmp1
}
define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
; CHECK-LABEL: orrimm2s_lsl24:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
ret <2 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
; CHECK-LABEL: orrimm4s_lsl0:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
ret <4 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
; CHECK-LABEL: orrimm4s_lsl8:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
ret <4 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
; CHECK-LABEL: orrimm4s_lsl16:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
ret <4 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
; CHECK-LABEL: orrimm4s_lsl24:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
ret <4 x i32> %tmp1
}
define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
; CHECK-LABEL: orrimm4h_lsl0:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
ret <4 x i16> %tmp1
}
define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
; CHECK-LABEL: orrimm4h_lsl8:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
ret <4 x i16> %tmp1
}
define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
; CHECK-LABEL: orrimm8h_lsl0:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
ret <8 x i16> %tmp1
}
define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
; CHECK-LABEL: orrimm8h_lsl8:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
ret <8 x i16> %tmp1
}
define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
; CHECK-LABEL: bicimm2s_lsl0:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #16
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
ret <2 x i32> %tmp1
}
define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
; CHECK-LABEL: bicimm2s_lsl8:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #16, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
ret <2 x i32> %tmp1
}
define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
; CHECK-LABEL: bicimm2s_lsl16:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #16, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
ret <2 x i32> %tmp1
}
define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
; CHECK-LABEL: bicimm2s_lsl124:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #16, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
ret <2 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
; CHECK-LABEL: bicimm4s_lsl0:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #16
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
ret <4 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
; CHECK-LABEL: bicimm4s_lsl8:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #16, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
ret <4 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
; CHECK-LABEL: bicimm4s_lsl16:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #16, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
ret <4 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
; CHECK-LABEL: bicimm4s_lsl124:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #16, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
ret <4 x i32> %tmp1
}
define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
; CHECK-LABEL: bicimm4h_lsl0_a:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #16
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
ret <4 x i16> %tmp1
}
define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
; CHECK-LABEL: bicimm4h_lsl0_b:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
ret <4 x i16> %tmp1
}
define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
; CHECK-LABEL: bicimm4h_lsl8_a:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #16, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
ret <4 x i16> %tmp1
}
define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
; CHECK-LABEL: bicimm4h_lsl8_b:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
ret <4 x i16> %tmp1
}
define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
; CHECK-LABEL: bicimm8h_lsl0_a:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #16
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
ret <8 x i16> %tmp1
@@ -274,14 +351,18 @@ define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
; CHECK-LABEL: bicimm8h_lsl0_b:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
ret <8 x i16> %tmp1
}
define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
; CHECK-LABEL: bicimm8h_lsl8_a:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #16, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
ret <8 x i16> %tmp1
@@ -289,133 +370,171 @@ define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
; CHECK-LABEL: bicimm8h_lsl8_b:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %tmp1
}
define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: and2xi32:
-; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, %b;
ret <2 x i32> %tmp1
}
define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: and4xi16:
-; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, %b;
ret <4 x i16> %tmp1
}
define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-LABEL: and1xi64:
-; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, %b;
ret <1 x i64> %tmp1
}
define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: and4xi32:
-; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, %b;
ret <4 x i32> %tmp1
}
define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: and8xi16:
-; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, %b;
ret <8 x i16> %tmp1
}
define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: and2xi64:
-; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, %b;
ret <2 x i64> %tmp1
}
define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: orr2xi32:
-; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, %b;
ret <2 x i32> %tmp1
}
define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: orr4xi16:
-; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, %b;
ret <4 x i16> %tmp1
}
define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-LABEL: orr1xi64:
-; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, %b;
ret <1 x i64> %tmp1
}
define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: orr4xi32:
-; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, %b;
ret <4 x i32> %tmp1
}
define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: orr8xi16:
-; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, %b;
ret <8 x i16> %tmp1
}
define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: orr2xi64:
-; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, %b;
ret <2 x i64> %tmp1
}
define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: eor2xi32:
-; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <2 x i32> %a, %b;
ret <2 x i32> %tmp1
}
define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: eor4xi16:
-; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <4 x i16> %a, %b;
ret <4 x i16> %tmp1
}
define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-LABEL: eor1xi64:
-; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <1 x i64> %a, %b;
ret <1 x i64> %tmp1
}
define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: eor4xi32:
-; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <4 x i32> %a, %b;
ret <4 x i32> %tmp1
}
define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: eor8xi16:
-; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <8 x i16> %a, %b;
ret <8 x i16> %tmp1
}
define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: eor2xi64:
-; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <2 x i64> %a, %b;
ret <2 x i64> %tmp1
}
@@ -423,7 +542,9 @@ define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: bic2xi32:
-; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
%tmp2 = and <2 x i32> %a, %tmp1
ret <2 x i32> %tmp2
@@ -431,7 +552,9 @@ define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: bic4xi16:
-; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
%tmp2 = and <4 x i16> %a, %tmp1
ret <4 x i16> %tmp2
@@ -439,7 +562,9 @@ define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-LABEL: bic1xi64:
-; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <1 x i64> %b, < i64 -1>
%tmp2 = and <1 x i64> %a, %tmp1
ret <1 x i64> %tmp2
@@ -447,7 +572,9 @@ define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: bic4xi32:
-; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
%tmp2 = and <4 x i32> %a, %tmp1
ret <4 x i32> %tmp2
@@ -455,7 +582,9 @@ define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: bic8xi16:
-; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp2 = and <8 x i16> %a, %tmp1
ret <8 x i16> %tmp2
@@ -463,7 +592,9 @@ define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: bic2xi64:
-; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
%tmp2 = and <2 x i64> %a, %tmp1
ret <2 x i64> %tmp2
@@ -471,7 +602,9 @@ define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: orn2xi32:
-; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
%tmp2 = or <2 x i32> %a, %tmp1
ret <2 x i32> %tmp2
@@ -479,7 +612,9 @@ define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: orn4xi16:
-; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
%tmp2 = or <4 x i16> %a, %tmp1
ret <4 x i16> %tmp2
@@ -487,7 +622,9 @@ define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-LABEL: orn1xi64:
-; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
%tmp1 = xor <1 x i64> %b, < i64 -1>
%tmp2 = or <1 x i64> %a, %tmp1
ret <1 x i64> %tmp2
@@ -495,7 +632,9 @@ define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: orn4xi32:
-; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
%tmp2 = or <4 x i32> %a, %tmp1
ret <4 x i32> %tmp2
@@ -503,7 +642,9 @@ define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: orn8xi16:
-; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp2 = or <8 x i16> %a, %tmp1
ret <8 x i16> %tmp2
@@ -511,7 +652,9 @@ define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: orn2xi64:
-; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
%tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
%tmp2 = or <2 x i64> %a, %tmp1
ret <2 x i64> %tmp2
@@ -519,8 +662,11 @@ define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: bsl2xi32_const:
-; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffffffff
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x000000ffffffff
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
%tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
%tmp3 = or <2 x i32> %tmp1, %tmp2
@@ -530,8 +676,11 @@ define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: bsl4xi16_const:
-; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff0000ffff
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
%tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
%tmp3 = or <4 x i16> %tmp1, %tmp2
@@ -540,8 +689,11 @@ define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
; CHECK-LABEL: bsl1xi64_const:
-; CHECK: movi {{d[0-9]+}}, #0xffffffffffffff00
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0xffffffffffffff00
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 -256 >
%tmp2 = and <1 x i64> %b, < i64 255 >
%tmp3 = or <1 x i64> %tmp1, %tmp2
@@ -550,8 +702,11 @@ define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: bsl4xi32_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
%tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
%tmp3 = or <4 x i32> %tmp1, %tmp2
@@ -560,8 +715,11 @@ define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: bsl8xi16_const:
-; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
%tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
%tmp3 = or <8 x i16> %tmp1, %tmp2
@@ -570,7 +728,12 @@ define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: bsl2xi64_const:
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI75_0
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI75_0]
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
%tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
%tmp3 = or <2 x i64> %tmp1, %tmp2
@@ -580,7 +743,9 @@ define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
; CHECK-LABEL: bsl8xi8:
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%1 = and <8 x i8> %v1, %v2
%2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%3 = and <8 x i8> %2, %v3
@@ -590,7 +755,9 @@ define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
; CHECK-LABEL: bsl4xi16:
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%1 = and <4 x i16> %v1, %v2
%2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
%3 = and <4 x i16> %2, %v3
@@ -600,7 +767,9 @@ define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
; CHECK-LABEL: bsl2xi32:
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%1 = and <2 x i32> %v1, %v2
%2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
%3 = and <2 x i32> %2, %v3
@@ -610,7 +779,9 @@ define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
; CHECK-LABEL: bsl1xi64:
-; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%1 = and <1 x i64> %v1, %v2
%2 = xor <1 x i64> %v1, <i64 -1>
%3 = and <1 x i64> %2, %v3
@@ -620,7 +791,9 @@ define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
; CHECK-LABEL: bsl16xi8:
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
%1 = and <16 x i8> %v1, %v2
%2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%3 = and <16 x i8> %2, %v3
@@ -630,7 +803,9 @@ define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
; CHECK-LABEL: bsl8xi16:
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
%1 = and <8 x i16> %v1, %v2
%2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%3 = and <8 x i16> %2, %v3
@@ -640,7 +815,9 @@ define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
; CHECK-LABEL: bsl4xi32:
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
%1 = and <4 x i32> %v1, %v2
%2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
%3 = and <4 x i32> %2, %v3
@@ -650,25 +827,33 @@ define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
define <8 x i8> @vselect_v8i8(<8 x i8> %a) {
; CHECK-LABEL: vselect_v8i8:
-; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff
-; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0x0000000000ffff
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: orr v0.2s, #0
+; CHECK-NEXT: ret
%b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i8> %b
}
define <4 x i16> @vselect_v4i16(<4 x i16> %a) {
; CHECK-LABEL: vselect_v4i16:
-; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff
-; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0x0000000000ffff
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: orr v0.2s, #0
+; CHECK-NEXT: ret
%b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0>
ret <4 x i16> %b
}
define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK-LABEL: vselect_cmp_ne:
-; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: mvn v0.8b, v0.8b
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%cmp = icmp ne <8 x i8> %a, %b
%d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
ret <8 x i8> %d
@@ -676,8 +861,10 @@ define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK-LABEL: vselect_cmp_eq:
-; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%cmp = icmp eq <8 x i8> %a, %b
%d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
ret <8 x i8> %d
@@ -685,9 +872,11 @@ define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK-LABEL: vselect_cmpz_ne:
-; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
-; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: mvn v0.8b, v0.8b
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%cmp = icmp ne <8 x i8> %a, zeroinitializer
%d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
ret <8 x i8> %d
@@ -695,8 +884,10 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK-LABEL: vselect_cmpz_eq:
-; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
-; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%cmp = icmp eq <8 x i8> %a, zeroinitializer
%d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
ret <8 x i8> %d
@@ -704,8 +895,10 @@ define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
; CHECK-LABEL: vselect_tst:
-; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmtst v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%tmp3 = and <8 x i8> %a, %b
%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
%d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c
@@ -714,7 +907,9 @@ define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
; CHECK-LABEL: bsl2xi64:
-; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
%1 = and <2 x i64> %v1, %v2
%2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
%3 = and <2 x i64> %2, %v3
@@ -724,84 +919,108 @@ define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
; CHECK-LABEL: orrimm8b_as_orrimm4h_lsl0:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255
+; CHECK-NEXT: ret
%val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <8 x i8> %val
}
define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
; CHECK-LABEL: orrimm8b_as_orimm4h_lsl8:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %val
}
define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
; CHECK-LABEL: orimm16b_as_orrimm8h_lsl0:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255
+; CHECK-NEXT: ret
%val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <16 x i8> %val
}
define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
; CHECK-LABEL: orimm16b_as_orrimm8h_lsl8:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %val
}
define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
; CHECK-LABEL: and8imm2s_lsl0:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
ret <8 x i8> %tmp1
}
define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
; CHECK-LABEL: and8imm2s_lsl8:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
ret <8 x i8> %tmp1
}
define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
; CHECK-LABEL: and8imm2s_lsl16:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
ret <8 x i8> %tmp1
}
define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
; CHECK-LABEL: and8imm2s_lsl24:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #254, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
ret <8 x i8> %tmp1
}
define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
; CHECK-LABEL: and16imm2s_lsl0:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
ret <4 x i16> %tmp1
}
define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
; CHECK-LABEL: and16imm2s_lsl8:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
ret <4 x i16> %tmp1
}
define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
; CHECK-LABEL: and16imm2s_lsl16:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
ret <4 x i16> %tmp1
}
define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
; CHECK-LABEL: and16imm2s_lsl24:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #254, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
ret <4 x i16> %tmp1
}
@@ -809,448 +1028,576 @@ define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
; CHECK-LABEL: and64imm2s_lsl0:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 -1095216660736>
ret <1 x i64> %tmp1
}
define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
; CHECK-LABEL: and64imm2s_lsl8:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 -280375465148161>
ret <1 x i64> %tmp1
}
define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
; CHECK-LABEL: and64imm2s_lsl16:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
ret <1 x i64> %tmp1
}
define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
; CHECK-LABEL: and64imm2s_lsl24:
-; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.2s, #254, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 144115183814443007>
ret <1 x i64> %tmp1
}
define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
; CHECK-LABEL: and8imm4s_lsl0:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
ret <16 x i8> %tmp1
}
define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
; CHECK-LABEL: and8imm4s_lsl8:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
ret <16 x i8> %tmp1
}
define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
; CHECK-LABEL: and8imm4s_lsl16:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
ret <16 x i8> %tmp1
}
define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
; CHECK-LABEL: and8imm4s_lsl24:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #254, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
ret <16 x i8> %tmp1
}
define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
; CHECK-LABEL: and16imm4s_lsl0:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
ret <8 x i16> %tmp1
}
define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
; CHECK-LABEL: and16imm4s_lsl8:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
ret <8 x i16> %tmp1
}
define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
; CHECK-LABEL: and16imm4s_lsl16:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
ret <8 x i16> %tmp1
}
define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
; CHECK-LABEL: and16imm4s_lsl24:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #254, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
ret <8 x i16> %tmp1
}
define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
; CHECK-LABEL: and64imm4s_lsl0:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
ret <2 x i64> %tmp1
}
define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
; CHECK-LABEL: and64imm4s_lsl8:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
ret <2 x i64> %tmp1
}
define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
; CHECK-LABEL: and64imm4s_lsl16:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
ret <2 x i64> %tmp1
}
define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
; CHECK-LABEL: and64imm4s_lsl24:
-; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4s, #254, lsl #24
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
ret <2 x i64> %tmp1
}
define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
; CHECK-LABEL: and8imm4h_lsl0:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %tmp1
}
define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
; CHECK-LABEL: and8imm4h_lsl8:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <8 x i8> %tmp1
}
define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
; CHECK-LABEL: and16imm4h_lsl0:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
ret <2 x i32> %tmp1
}
define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
; CHECK-LABEL: and16imm4h_lsl8:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
ret <2 x i32> %tmp1
}
define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
; CHECK-LABEL: and64imm4h_lsl0:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
ret <1 x i64> %tmp1
}
define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
; CHECK-LABEL: and64imm4h_lsl8:
-; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <1 x i64> %a, < i64 71777214294589695>
ret <1 x i64> %tmp1
}
define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
; CHECK-LABEL: and8imm8h_lsl0:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
ret <16 x i8> %tmp1
}
define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
; CHECK-LABEL: and8imm8h_lsl8:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
ret <16 x i8> %tmp1
}
define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
; CHECK-LABEL: and16imm8h_lsl0:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
ret <4 x i32> %tmp1
}
define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
; CHECK-LABEL: and16imm8h_lsl8:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
ret <4 x i32> %tmp1
}
define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
; CHECK-LABEL: and64imm8h_lsl0:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
ret <2 x i64> %tmp1
}
define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
; CHECK-LABEL: and64imm8h_lsl8:
-; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
ret <2 x i64> %tmp1
}
define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
; CHECK-LABEL: orr8imm2s_lsl0:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
ret <8 x i8> %tmp1
}
define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
; CHECK-LABEL: orr8imm2s_lsl8:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
ret <8 x i8> %tmp1
}
define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
; CHECK-LABEL: orr8imm2s_lsl16:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
ret <8 x i8> %tmp1
}
define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
; CHECK-LABEL: orr8imm2s_lsl24:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
ret <8 x i8> %tmp1
}
define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
; CHECK-LABEL: orr16imm2s_lsl0:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
ret <4 x i16> %tmp1
}
define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
; CHECK-LABEL: orr16imm2s_lsl8:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
ret <4 x i16> %tmp1
}
define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
; CHECK-LABEL: orr16imm2s_lsl16:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
ret <4 x i16> %tmp1
}
define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
; CHECK-LABEL: orr16imm2s_lsl24:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
ret <4 x i16> %tmp1
}
define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
; CHECK-LABEL: orr64imm2s_lsl0:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, < i64 1095216660735>
ret <1 x i64> %tmp1
}
define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
; CHECK-LABEL: orr64imm2s_lsl8:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, < i64 280375465148160>
ret <1 x i64> %tmp1
}
define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
; CHECK-LABEL: orr64imm2s_lsl16:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, < i64 71776119077928960>
ret <1 x i64> %tmp1
}
define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
; CHECK-LABEL: orr64imm2s_lsl24:
-; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.2s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
ret <1 x i64> %tmp1
}
define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
; CHECK-LABEL: orr8imm4s_lsl0:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
ret <16 x i8> %tmp1
}
define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
; CHECK-LABEL: orr8imm4s_lsl8:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
ret <16 x i8> %tmp1
}
define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
; CHECK-LABEL: orr8imm4s_lsl16:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
ret <16 x i8> %tmp1
}
define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
; CHECK-LABEL: orr8imm4s_lsl24:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
ret <16 x i8> %tmp1
}
define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
; CHECK-LABEL: orr16imm4s_lsl0:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
ret <8 x i16> %tmp1
}
define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
; CHECK-LABEL: orr16imm4s_lsl8:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
ret <8 x i16> %tmp1
}
define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
; CHECK-LABEL: orr16imm4s_lsl16:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
ret <8 x i16> %tmp1
}
define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
; CHECK-LABEL: orr16imm4s_lsl24:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
ret <8 x i16> %tmp1
}
define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
; CHECK-LABEL: orr64imm4s_lsl0:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
ret <2 x i64> %tmp1
}
define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
; CHECK-LABEL: orr64imm4s_lsl8:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
ret <2 x i64> %tmp1
}
define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
; CHECK-LABEL: orr64imm4s_lsl16:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #16
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
ret <2 x i64> %tmp1
}
define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
; CHECK-LABEL: orr64imm4s_lsl24:
-; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4s, #255, lsl #24
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
ret <2 x i64> %tmp1
}
define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
; CHECK-LABEL: orr8imm4h_lsl0:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <8 x i8> %tmp1
}
define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
; CHECK-LABEL: orr8imm4h_lsl8:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %tmp1
}
define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
; CHECK-LABEL: orr16imm4h_lsl0:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
ret <2 x i32> %tmp1
}
define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
; CHECK-LABEL: orr16imm4h_lsl8:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
ret <2 x i32> %tmp1
}
define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
; CHECK-LABEL: orr64imm4h_lsl0:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, < i64 71777214294589695>
ret <1 x i64> %tmp1
}
define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
; CHECK-LABEL: orr64imm4h_lsl8:
-; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.4h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
ret <1 x i64> %tmp1
}
define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
; CHECK-LABEL: orr8imm8h_lsl0:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <16 x i8> %tmp1
}
define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
; CHECK-LABEL: orr8imm8h_lsl8:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %tmp1
}
define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
; CHECK-LABEL: orr16imm8h_lsl0:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
ret <4 x i32> %tmp1
}
define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
; CHECK-LABEL: orr16imm8h_lsl8:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
ret <4 x i32> %tmp1
}
define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
; CHECK-LABEL: orr64imm8h_lsl0:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
ret <2 x i64> %tmp1
}
define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
; CHECK-LABEL: orr64imm8h_lsl8:
-; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr v0.8h, #255, lsl #8
+; CHECK-NEXT: ret
%tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
ret <2 x i64> %tmp1
}
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