[PATCH] D74338: [RFC][TableGen/RISCV] Support combining AssemblerPredicates with ORs

[Simon Cook via Phabricator via llvm-commits]

simoncook updated this revision to Diff 244464.
simoncook added a comment.

Add test for RISCV Instruction Compression, so now all uses of `AssemblerCondString` are covered by this patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74338/new/

https://reviews.llvm.org/D74338

Files:
  llvm/include/llvm/MC/MCInstPrinter.h
  llvm/include/llvm/Target/Target.td
  llvm/lib/MC/MCInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/test/TableGen/AsmPredicateCombining.td
  llvm/test/TableGen/AsmPredicateCombiningRISCV.td
  llvm/utils/TableGen/AsmWriterEmitter.cpp
  llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
  llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
  llvm/utils/TableGen/SubtargetFeatureInfo.cpp

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