[PATCH] D74349: [PowerPC][AIX] Spill and restore the non-volatile condition register bits.

[Sean Fertile via Phabricator via llvm-commits]

sfertile added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir:10
+
+# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr7 \
+# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
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Xiangling_L wrote:
> Usually, the default cpu level we set in the testcase is `pwr4`, can I ask why we want to test `pwr7` here instead?
Its just to match the ELF V1 runstep. There should be no particular difference between pwr4 and pwr7 for this test.


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Comment at: llvm/test/CodeGen/PowerPC/ppc64-crsave.mir:15
+# TODO FIXME: We only check the save and restores of the callee saved gpr for
+# ELF becuase AIX callee saved registers haven't been properly implemented yet.
+
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Xiangling_L wrote:
> In case we might forget to update the testcase when we support AIX, can we leave an assertion in the code instead?
In what code? 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D74349/new/

https://reviews.llvm.org/D74349