[PATCH] D74492: [AArch64] Fix BTI landing pad generation.

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd5a186a60014: [AArch64] Fix BTI landing pad generation. (authored by danielkiss, committed by ostannard).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74492/new/

https://reviews.llvm.org/D74492

Files:
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/test/CodeGen/AArch64/branch-target-enforcement.mir


Index: llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
===================================================================
--- llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
+++ llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
@@ -97,6 +97,12 @@
     ret i32 %merge2
   }
 
+  define hidden i32 @debug_ptr_auth() "branch-target-enforcement" {
+  entry:
+    tail call void asm sideeffect "", "~{lr}"()
+    ret i32 0
+  }
+
 ...
 ---
 # External function, could be addres-taken elsewhere so needs BTI JC.
@@ -321,5 +327,30 @@
     renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.return), 0
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store 8 into @label_address.addr)
     RET undef $lr, implicit killed $w0
+---
+# When PACIASP is the first real instruction in the functions then BTI should not be inserted.
+name:            debug_ptr_auth
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; CHECK-LABEL: name: debug_ptr_auth
+    ; CHECK-NOT: HINT
+    ; CHECK: DBG_VALUE
+    ; CHECK: frame-setup PACIASP
+    ; CHECK-NOT: HINT
+    ; CHECK: RETAA
+    DBG_VALUE $lr
+    frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-setup CFI_INSTRUCTION negate_ra_sign_state
+    early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store 8 into %stack.0)
+    INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
+    $w0 = ORRWrs $wzr, $wzr, 0
+    early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load 8 from %stack.0)
+    RETAA implicit $sp, implicit $lr, implicit killed $w0
 
 ...
Index: llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
+++ llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
@@ -118,6 +118,10 @@
 
   auto MBBI = MBB.begin();
 
+  // Skip the meta instuctions, those will be removed anyway.
+  for (; MBBI != MBB.end() && MBBI->isMetaInstruction(); ++MBBI)
+    ;
+
   // PACI[AB]SP are implicitly BTI JC, so no BTI instruction needed there.
   if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP ||
                             MBBI->getOpcode() == AArch64::PACIBSP))


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