[PATCH] D74524: [Scheduling] Improve memory ops cluster preparation

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: PowerPC, fhahn, evandro, arsenm.
Herald added subscribers: llvm-commits, kerbowa, arphaman, javed.absar, hiraditya, nhaehnle, wdng, jvesely, MatzeB.
Herald added a project: LLVM.
qiucf edited the summary of this revision.

SUnits in `ScheduleDAGInstrs` will be divided into several groups by their ctrl pred node number. Scheduler tries to build possible cluster edges inside each group. However, there're some units with no ctrl preds.

This patch

1. Add these preds to each group before `clusterNeighboringMemOps`, to catch more cluster opportunities.
2. Add a bitmap to mark units already clustered, remove them before `clusterNeighboringMemOps`

This impacts several test cases, by comparing scheduling log, we can find more cluster edges added and they are scheduled together.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74524

Files:
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
  llvm/test/CodeGen/AMDGPU/global-saddr.ll
  llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
  llvm/test/CodeGen/AMDGPU/sign_extend.ll

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