[PATCH] D74254: [llvm][aarch64] SVE addressing modes.

Wed Feb 12 13:47:06 PST 2020

fpetrogalli added a comment.

I have uploaded PDF renderings of the DAGS before and after the changes. I am not sure the tests for the combiner are explicit about the fact that the combiner is run on this pattern, but the graphs attached here show the effect of my changes on the code. I think that some of the patterns that are needed to show the changes in the output code are missing.

F11333296: before.dag.combine_sub_vscale_i64-bdd206.dot.pdf <https://reviews.llvm.org/F11333296>

F11333295: after.dag.combine_sub_vscale_i64-7f807e.dot.pdf <https://reviews.llvm.org/F11333295>

F11333294: before.dag.combine_mul_vscale_i64-f4259d.dot.pdf <https://reviews.llvm.org/F11333294>

F11333293: before.dag.combine_add_vscale_i64-62fd59.dot.pdf <https://reviews.llvm.org/F11333293>

F11333292: after.dag.combine_mul_vscale_i64-975c2a.dot.pdf <https://reviews.llvm.org/F11333292>

F11333291: after.dag.combine_add_vscale_i64-35445c.dot.pdf <https://reviews.llvm.org/F11333291>

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74254/new/

https://reviews.llvm.org/D74254