[PATCH] D74444: [NVPTX, LSV] Move the LSV optimization pass to later when the graph is cleaner
Frederic Bastien via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 12 11:56:47 PST 2020
nouiz updated this revision to Diff 244243.
nouiz added a comment.
I simplified the test. As it was way simpler, I added it to an existing test file.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D74444/new/
https://reviews.llvm.org/D74444
Files:
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
llvm/test/CodeGen/NVPTX/vector-loads.ll
Index: llvm/test/CodeGen/NVPTX/vector-loads.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/vector-loads.ll
+++ llvm/test/CodeGen/NVPTX/vector-loads.ll
@@ -64,3 +64,39 @@
store <8 x i32> %t2, <8 x i32>* %a
ret void
}
+
+; The following test wasn't passing previously as the address
+; computation was still too complex when LSV was called.
+declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
+define void @foo_complex(i8* nocapture readonly align 16 dereferenceable(134217728) %alloc0) {
+; CHECK: .func foo_complex
+; CHECK: ld.v2.u8
+; CHECK-NOT: ld
+; CHECK: ret
+ %targ0.1.typed = bitcast i8* %alloc0 to [1024 x [131072 x i8]]*
+ %t0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !1
+ %t1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
+ %t2 = lshr i32 %t1, 8
+ %t3 = shl nuw nsw i32 %t1, 9
+ %ttile_origin.2 = and i32 %t3, 130560
+ %tstart_offset_x_mul = shl nuw nsw i32 %t0, 1
+ %t4 = or i32 %ttile_origin.2, %tstart_offset_x_mul
+ %t6 = or i32 %t4, 1
+ %t8 = or i32 %t4, 128
+ %t9 = zext i32 %t8 to i64
+ %t10 = or i32 %t4, 129
+ %t11 = zext i32 %t10 to i64
+ %t20 = zext i32 %t2 to i64
+ %t27 = getelementptr inbounds [1024 x [131072 x i8]], [1024 x [131072 x i8]]* %targ0.1.typed, i64 0, i64 %t20, i64 %t9
+ %t28 = load i8, i8* %t27, align 2
+ %t31 = getelementptr inbounds [1024 x [131072 x i8]], [1024 x [131072 x i8]]* %targ0.1.typed, i64 0, i64 %t20, i64 %t11
+ %t32 = load i8, i8* %t31, align 1
+ %t33 = icmp ult i8 %t28, %t32
+ %t34 = select i1 %t33, i8 %t32, i8 %t28
+ store i8 %t34, i8* %t31
+ ret void
+}
+
+
+!1 = !{i32 0, i32 64}
Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -276,8 +276,6 @@
addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
if (getOptLevel() != CodeGenOpt::None) {
addAddressSpaceInferencePasses();
- if (!DisableLoadStoreVectorizer)
- addPass(createLoadStoreVectorizerPass());
addStraightLineScalarOptimizationPasses();
}
@@ -295,8 +293,11 @@
// %1 = shl %a, 2
//
// but EarlyCSE can do neither of them.
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None) {
addEarlyCSEOrGVNPass();
+ if (!DisableLoadStoreVectorizer)
+ addPass(createLoadStoreVectorizerPass());
+ }
}
bool NVPTXPassConfig::addInstSelector() {
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