[llvm] ab4d606 - [PowerPC] Add support for intrinsic llvm.ppc.eieio

[Stefan Pintilie via llvm-commits]

Author: Anil Mahmud
Date: 2020-02-12T09:02:17-06:00
New Revision: ab4d60642142b369557adc83c9c51cec01b4b213

URL: https://github.com/llvm/llvm-project/commit/ab4d60642142b369557adc83c9c51cec01b4b213
DIFF: https://github.com/llvm/llvm-project/commit/ab4d60642142b369557adc83c9c51cec01b4b213.diff

LOG: [PowerPC] Add support for intrinsic llvm.ppc.eieio

Add support for the intrinsic llvm.ppc.eieio to emit the instruction eieio.

Differential Revision: https://reviews.llvm.org/D69066

Added: 
    llvm/test/CodeGen/PowerPC/eieio.ll

Modified: 
    llvm/include/llvm/IR/IntrinsicsPowerPC.td
    llvm/lib/Target/PowerPC/PPCInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index c2fac55528fe..f4ed7eb634da 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -35,6 +35,8 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_sync : Intrinsic<[], [], []>;
   // lwsync is sync 1
   def int_ppc_lwsync : Intrinsic<[], [], []>;
+  // eieio instruction
+  def int_ppc_eieio : Intrinsic<[],[],[]>;
 
   // Intrinsics used to generate ctr-based loops. These should only be
   // generated by the PowerPC backend!

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 08bc6c1502a9..e14d63613c89 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2325,10 +2325,15 @@ let isCodeGenOnly = 1 in {
   }
 }
 
+// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
+def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
+                                 "eieio", IIC_LdStLoad, []>;
+
 def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_eieio),  (EnforceIEIO)>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Arithmetic Instructions.
@@ -4176,10 +4181,6 @@ def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
                     "icbi $src", IIC_LdStICBI, []>;
 
-// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
-def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
-                           "eieio", IIC_LdStLoad, []>;
-
 def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
                          "wait $L", IIC_LdStLoad, []>;
 

diff  --git a/llvm/test/CodeGen/PowerPC/eieio.ll b/llvm/test/CodeGen/PowerPC/eieio.ll
new file mode 100644
index 000000000000..7600782067f5
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/eieio.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+define void @eieio_test() {
+; CHECK-LABEL: @eieio_test
+; CHECK: eieio
+; CHECK-NEXT: blr
+
+entry:
+  tail call void @llvm.ppc.eieio()
+  ret void
+}
+
+declare void @llvm.ppc.eieio()