[PATCH] D74485: [ARM] Fix ReconstructShuffle for bigendian

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham accepted this revision.
simon_tatham added a comment.
This revision is now accepted and ready to land.

LGTM, with a not-very-important comment nitpick.



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Comment at: llvm/lib/Target/ARM/ARMInstrInfo.td:313
+// whereas 'bitconvert' will map it to the high byte in big-endian mode,
+// because that's what VSTRH.16 followed by VLDRB.8 would do. So the bitconvert
+// would have to emit a VREV16.8 instruction, whereas the VECTOR_REG_CAST emits
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This reference to MVE-specific instruction names might be out of place now this comment is shared with NEON :-) But I don't know enough NEON to be sure of what the analogous load/store instructions there look like. Are those VST1 / VLD1, perhaps?


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