[PATCH] D74147: [AArch64] Add BIT/BIF support.

Wed Feb 12 04:23:26 PST 2020

ilinpv marked 2 inline comments as done.
ilinpv added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1346
   case AArch64ISD::BIT:               return "AArch64ISD::BIT";
+  case AArch64ISD::BIF:               return "AArch64ISD::BIF";
   case AArch64ISD::CBZ:               return "AArch64ISD::CBZ";
----------------
dmgreen wrote:
> Is this ever generated from anything?
> 
> AArch64ISD::BSL and AArch64ISD::BIT seem to be created from ISelLowering. Would it make sense to convert them to use BSLP as well? We could then presumably remove a lot of the explicit patterns for BSL, BIT and BIF.
It is not generated, just a manual target node name. BSL and BIF can be converted to use BSLP. However using BSLP for BIT in ISelLowering can lead to additional move generation on expansion, see vector-fcopysign as example.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:5213
+  : Pseudo<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), pattern>,
+    Sched<[WriteV]>;
+
----------------
dmgreen wrote:
> We should make sure that the schedules have info on BSLP, if they previously had explicit info for BSP/BIT/BIF.
Schedules using explicit regex "^(BIF|BIT|BSL)". As I understand it schedules passes happen after pseudo expansion, so at schedule stage we have all BSLP expanded to BIF/BIT/BSL.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74147/new/

https://reviews.llvm.org/D74147