[PATCH] D74427: [AArch64][GlobalISel] Properly implement widening for TB(N)Z
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 11 15:08:28 PST 2020
aemerson accepted this revision.
aemerson added a comment.
This revision is now accepted and ready to land.
LGTM with nits.
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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:5159
+Register
+AArch64InstructionSelector::widenIfNeeded(Register Reg, unsigned WideSize,
+ MachineIRBuilder &MIB) const {
----------------
I think this should be named something more specific, like widenGPRBankRegIfNeeded or similar, because it's not a generic widening.
================
Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:5202
+ constrainSelectedInstRegOperands(*SubRegToReg, TII, TRI, RBI);
+ return SubRegToReg->getOperand(0).getReg();
+}
----------------
This can be SubRegToReg.getReg(0);
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D74427/new/
https://reviews.llvm.org/D74427
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