[PATCH] D74370: [mlir] [VectorOps] Implement vector.reduce operation

[River Riddle via Phabricator via llvm-commits]

rriddle added inline comments.


================
Comment at: mlir/include/mlir/Dialect/VectorOps/VectorOps.td:203
+    ```
+      %1 = vector.reduction "add", %0 : vector<16xf32>
+
----------------
Looks like you are missing the `into type` on these examples.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74370/new/

https://reviews.llvm.org/D74370