[PATCH] D74306: [MIR][ARM] WIP: Print condition code names instead of magic constants

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: ostannard, efriedma, samparker, dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

I spent a day hacking because, well, I guess you have the same like me: I will probably never forget that 14 means "Always", but what do the other 14 condition codes mean? This is a work-in-progress patch to change the MIR printer and parser to change and accept instead of e.g. this:

  dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg
  t2Bcc %bb.4, 0, killed $cpsr

This instead:

  dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, cond:always, $noreg
  t2Bcc %bb.4, cond:equal, killed $cpsr
      

This shows that for this example we now print `cond:always` and `cond:equal` instead of magic constants `14` and `0`, respectively.

I have given it some thoughts to a new MachineOperand type for this: instead of an immediate type, create a proper type for it, with a `print` method, but that seems like a whole lot of changes to me, with the only benefit of printing, so not really worth it. Just a translation from the textual form to a constant, and vice versa, is the easiest.

If we like this idea, we can further discuss:

- how to deploy this. If you run the test suite with this change, all .mir tests in the ARM directory will obviously fail because we now print the names instead of magic constants. I could do a batch update of all the ARM .mir tests to fix this. The alternative is to enable printing names first under an option, but that doesn't seem attractive to me because then you need to enable it and we don't really see the benefit.
- Of course I am open for bikeshedding names, syntax, and the rest too, as I said this is a WIP mainly to demonstrate the idea.


https://reviews.llvm.org/D74306

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MIRPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir

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