[llvm] 7f5b3fa - [X86][SSE] Add X86ISD::FRCP handling to isNegatibleForFree

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-02-08T10:56:27Z
New Revision: 7f5b3fa73c39be2491a74283080a35b7140972d3

URL: https://github.com/llvm/llvm-project/commit/7f5b3fa73c39be2491a74283080a35b7140972d3
DIFF: https://github.com/llvm/llvm-project/commit/7f5b3fa73c39be2491a74283080a35b7140972d3.diff

LOG: [X86][SSE] Add X86ISD::FRCP handling to isNegatibleForFree

Peek through X86ISD::FRCP nodes to see if there is a negatible input.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/fma-fneg-combine-2.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dce76b6d728c..85741ca1c057 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -42941,6 +42941,9 @@ char X86TargetLowering::isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
     }
     return 1;
   }
+  case X86ISD::FRCP:
+    return isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
+                              ForCodeSize, Depth + 1);
   }
 
   return TargetLowering::isNegatibleForFree(Op, DAG, LegalOperations,
@@ -42994,6 +42997,11 @@ SDValue X86TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
         NewOps[i] = Op.getOperand(i);
     return DAG.getNode(NewOpc, SDLoc(Op), VT, NewOps);
   }
+  case X86ISD::FRCP:
+    return DAG.getNode(Opc, SDLoc(Op), VT,
+                       getNegatedExpression(Op.getOperand(0), DAG,
+                                            LegalOperations, ForCodeSize,
+                                            Depth + 1));
   }
 
   return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations,

diff  --git a/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll b/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
index 3aadee8a317e..0b66d53f5ac9 100644
--- a/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
+++ b/llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
@@ -89,16 +89,14 @@ entry:
 define <4 x float> @test_fma_rcp_fneg_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z)  {
 ; FMA3-LABEL: test_fma_rcp_fneg_v4f32:
 ; FMA3:       # %bb.0: # %entry
-; FMA3-NEXT:    vxorps {{.*}}(%rip), %xmm2, %xmm2
 ; FMA3-NEXT:    vrcpps %xmm2, %xmm2
-; FMA3-NEXT:    vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
+; FMA3-NEXT:    vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
 ; FMA3-NEXT:    retq
 ;
 ; FMA4-LABEL: test_fma_rcp_fneg_v4f32:
 ; FMA4:       # %bb.0: # %entry
-; FMA4-NEXT:    vxorps {{.*}}(%rip), %xmm2, %xmm2
 ; FMA4-NEXT:    vrcpps %xmm2, %xmm2
-; FMA4-NEXT:    vfmaddps %xmm2, %xmm1, %xmm0, %xmm0
+; FMA4-NEXT:    vfmsubps %xmm2, %xmm1, %xmm0, %xmm0
 ; FMA4-NEXT:    retq
 entry:
   %0 = fneg <4 x float> %z