[PATCH] D74254: [WIP][llvm][aarch64] SVE addressing modes: register + immediate.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.

Tests are covering all `llvm.masked.load` and `llvm.masked.store` intrinsics, including zero and sign extended loads, and trucating stores.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74254

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg+imm.ll

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