[PATCH] D73339: [RISCV] Compress instructions based on function features

[Luís Marques via Phabricator via llvm-commits]

luismarques added a comment.

Copying the the STI isn't quite trivial, and we're only using a small subset of what it provides, in `compressInst`. Can't this be done more tightly?

`compressInst` calls `RISCVValidateMCOperand`, which checks things like `STI.getTargetTriple().isArch64Bit()`. You said that "under LTO it is common to not specify the architecture". If that includes not properly initializing the STI target triple then those checks will fail in some circumstances. Please check also the status of the other members of the STI, in case the validation ends up using them in the future.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D73339/new/

https://reviews.llvm.org/D73339