[PATCH] D74239: [Hexagon] v67+ HVX register pairs should support either direction
Brian Cain via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 10:17:43 PST 2020
bcain created this revision.
bcain added reviewers: kparzysz, bcahoon, shankare.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
Assembler now permits pairs like 'v0:1', which are encoded
differently from the odd-first pairs like 'v1:0'.
The compiler will require more work to leverage these new register
pairs.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D74239
Files:
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
llvm/test/CodeGen/Hexagon/swp-sigma.ll
llvm/test/CodeGen/Hexagon/vect-regpairs.ll
llvm/test/MC/Hexagon/hvx-swapped-regpairs-alias-neg.s
llvm/test/MC/Hexagon/hvx-swapped-regpairs.s
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