[PATCH] D74147: [AArch64] Add BIT/BIF support.

Fri Feb 7 09:58:52 PST 2020

dmgreen added subscribers: greened, dmgreen.
dmgreen edited reviewers, added: dmgreen; removed: greened.
dmgreen added a comment.

Can you update with all the context? -U999999. It helps to be able to see the entire file here in phabricator, which would not otherwise be available.

For these tests that have changed/been added, can you run the update_llc_test_checks scripts on them all and commit that as a separate initial (NFC) patch? That way the differences here are more obvious. It looks like a nice improvement, but it's hard to tell when the test just says "CHECK: bsl"

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1346
   case AArch64ISD::BIT:               return "AArch64ISD::BIT";
+  case AArch64ISD::BIF:               return "AArch64ISD::BIF";
   case AArch64ISD::CBZ:               return "AArch64ISD::CBZ";
----------------
Is this ever generated from anything?

AArch64ISD::BSL and AArch64ISD::BIT seem to be created from ISelLowering. Would it make sense to convert them to use BSLP as well? We could then presumably remove a lot of the explicit patterns for BSL, BIT and BIF.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:5213
+  : Pseudo<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), pattern>,
+    Sched<[WriteV]>;
+
----------------
We should make sure that the schedules have info on BSLP, if they previously had explicit info for BSP/BIT/BIF.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74147/new/

https://reviews.llvm.org/D74147