[PATCH] D74165: [x86] [DAGCombine] Prefer shifts of constant widths.

[Justin Lebar via Phabricator via llvm-commits]

jlebar created this revision.
jlebar added a reviewer: bkramer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.

Commute shift and select in the following pattern:

  shift lhs, (select cond, constant1, constant2) -->
  select cond, (shift lhs, constant1), (shift lhs, constant2)

This is beneficial on x86, where shifting by an immediate is faster than
shifting by a register.

Canonical example:

  return x << (cond ? 4 : 8);

before this patch

  mov     eax, edi
  xor     ecx, ecx
  test    esi, esi
  sete    cl
  lea     ecx, [rcx + 2*rcx]
  add     ecx, 3
  shl     eax, cl
  ret

after this patch

  lea     eax, [8*rdi]
  shl     edi, 6
  test    esi, esi
  cmove   eax, edi
  ret

I enabled this folding only on x86.  By my reading of the ARM Coretex-A75
optimization guide, this is not beneficial there.  (I didn't check other ARM
processors.)  I was unable to find a PPC optimization guide that listed
instruction latencies, so I didn't enable it there.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74165

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/X86/dagcombine-select.ll
  llvm/test/CodeGen/X86/dagcombine-shifts.ll
  llvm/test/CodeGen/X86/pr22338.ll
  llvm/test/CodeGen/X86/select.ll
  llvm/test/CodeGen/X86/shift-parts.ll

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