[PATCH] D74149: [AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

LGTM.



================
Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1235
+
+  // When we have a greater-than comparison, we can just test if the last bit
+  // is zero.
----------------
Instead of "last bit" which can be ambiguous, say "msb" or sign bit.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1259
 
-  // Try to fold things into the branch.
-  const auto Pred = (CmpInst::Predicate)CCMI->getOperand(1).getPredicate();
-  MachineInstr *LHSMI = getDefIgnoringCopies(LHS, MRI);
   if (tryOptAndIntoCompareBranch(LHSMI, VRegAndVal->Value, Pred, DestMBB,
                                  MIB)) {
----------------
Add an assert about VRegVal being 0 here? At the very least it makes it clearer what the preconditions are for the code below.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1265
 
   // When we have a less than comparison, we can just test if the last bit
   // is not zero.
----------------
Same thing here with 'last bit'.


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https://reviews.llvm.org/D74149