[PATCH] D74147: [AArch64] Add BIT/BIF support.
Pavel Iliin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 6 11:08:00 PST 2020
ilinpv created this revision.
ilinpv added reviewers: t.p.northover, greened, samparker.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.
This patch added generation of SIMD bitwise insert BIT/BIF instructions.
In the absence of GCC-like functionality for optimal constraints satisfaction during register allocation
the bitwise insert patterns are matched by pseudo BSLP instruction with not tied def.
It is expanded later after register allocation with def tied to BSL/BIT/BIF depending on operand's registers.
This allows to get rid of redundant moves.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D74147
Files:
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
llvm/test/CodeGen/AArch64/sat-add.ll
llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
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