[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:54
+    : SubtargetFeature<"v", "HasStdExtV", "true",
+                       "'V' (Vector Instructions)">;
+def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
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evandro wrote:
> Should it also imply `FeatureStdExtD`?
I didn't find that V will imply D extension. Could you indicate the description in spec about this?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:77
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+// load vd, (rs1), vm
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evandro wrote:
> No need to set fields to the default `0`.
There is no default value for hasSideEffects, mayLoad, and mayStore.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:534
+
+// Vector Fixed-Point Arithmetic Instructions
+defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>;
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evandro wrote:
> Shouldn't these have `vxsat` in `Defs`?
It should have no impact on CodeGen. It seems no instructions to use vxsat.


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  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987