[llvm] 043e478 - [PowerPC][NFC] Clang-format on commit 4b414d

[Victor Huang via llvm-commits]

Author: Victor Huang
Date: 2020-02-05T13:47:54-06:00
New Revision: 043e4787211609e987799050ba2944b77a53ddb5

URL: https://github.com/llvm/llvm-project/commit/043e4787211609e987799050ba2944b77a53ddb5
DIFF: https://github.com/llvm/llvm-project/commit/043e4787211609e987799050ba2944b77a53ddb5.diff

LOG: [PowerPC][NFC] Clang-format on commit 4b414d

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
    llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 343c0eb30382..ed98852088e7 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -356,9 +356,10 @@ struct PPCOperand : public MCParsedAsmOperand {
   bool isS16ImmX16() const { return Kind == Expression ||
                                     (Kind == Immediate && isInt<16>(getImm()) &&
                                      (getImm() & 15) == 0); }
-  bool isS34ImmX16() const { return Kind == Expression ||
-                                    (Kind == Immediate && isInt<34>(getImm()) &&
-                                    (getImm() & 15) == 0); }
+  bool isS34ImmX16() const {
+    return Kind == Expression ||
+           (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
+  }
   bool isS34Imm() const {
     // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
     // ContextImmediate is needed.

diff  --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index 911359264bdf..2ff3f5d65a03 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -469,7 +469,7 @@ void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &O) {
   printS34ImmOperand(MI, OpNo, O);
   O << '(';
-  printImmZeroOperand(MI, OpNo+1, O);
+  printImmZeroOperand(MI, OpNo + 1, O);
   O << ')';
 }
 
@@ -477,7 +477,7 @@ void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   printS34ImmOperand(MI, OpNo, O);
   O << '(';
-  printOperand(MI, OpNo+1, O);
+  printOperand(MI, OpNo + 1, O);
   O << ')';
 }
 

diff  --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
index 86c93ab60f3e..672f6e02ce93 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -183,9 +183,8 @@ PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
   // displacement and the next 5 bits as the register #.
   assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
-  uint64_t RegBits =
-    getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
-
+  uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
+                     << 34;
   const MCOperand &MO = MI.getOperand(OpNo);
   return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
 }