[llvm] f64b346 - [ARM] Add extra use test for MVE VPT blocks. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2020-02-05T18:32:18Z
New Revision: f64b3466b6bbea0422209ecaceecd361bb09ff87

URL: https://github.com/llvm/llvm-project/commit/f64b3466b6bbea0422209ecaceecd361bb09ff87
DIFF: https://github.com/llvm/llvm-project/commit/f64b3466b6bbea0422209ecaceecd361bb09ff87.diff

LOG: [ARM] Add extra use test for MVE VPT blocks. NFC

Added: 
    llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
new file mode 100644
index 000000000000..8d794a69760e
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8.1m.main-arm-none-eabi"
+
+  define arm_aapcs_vfpcc <4 x float> @vpt_preuse(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) #0 {
+  entry:
+    ;
+    ; Intentionally left blank, see the MIR sequence below.
+    ;
+    ret <4 x float> %inactive1
+  }
+
+  attributes #0 = { "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" }
+
+...
+---
+name:            vpt_preuse
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$q0', virtual-reg: '' }
+  - { reg: '$q1', virtual-reg: '' }
+  - { reg: '$q2', virtual-reg: '' }
+  - { reg: '$q5', virtual-reg: '' }
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+constants:       []
+body:             |
+  bb.0:
+  liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
+
+
+    ; CHECK-LABEL: name: vpt_preuse
+    ; CHECK: successors: %bb.0(0x80000000)
+    ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
+    ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg
+    ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
+    ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg
+    ; CHECK: BUNDLE implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $vpr, implicit killed $r4 {
+    ; CHECK:   MVE_VPST 8, implicit $vpr
+    ; CHECK:   renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr
+    ; CHECK: }
+    ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
+    ; CHECK: t2B %bb.0, 14, $noreg
+  renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg
+  renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
+  VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg
+  renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr
+  t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
+  t2B %bb.0, 14, $noreg
+
+...