[PATCH] D74074: [AArch64] Predictably disassemble system registers with the same encoding

[Momchil Velikov via Phabricator via llvm-commits]

chill created this revision.
chill added reviewers: t.p.northover, ostannard, sdesmalen.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.

The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers, defined by
separate extension specifications (ETM and ETE, respectively), yet they use the
same encoding in MSR/MRS.

When performing a system register lookup by encoding, we would essentially
return a random one, depending on the number, relative position in the TableGen
file, whether the TableGen records for system registers are named or not, and,
if they are named, depending on record (not register!) name as well.

This patch works around the issue by explictly checking for the
TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR.


https://reviews.llvm.org/D74074

Files:
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/test/MC/AArch64/ete-sysregs.s
  llvm/test/MC/AArch64/trace-regs.s
  llvm/test/MC/Disassembler/AArch64/ete.txt
  llvm/test/MC/Disassembler/AArch64/trace-regs.txt

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