[llvm] 01022af - [ARM][MVE] LowOverheadLoops: DCE on the iteration count setup expression
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 5 07:18:04 PST 2020
Author: Sjoerd Meijer
Date: 2020-02-05T15:15:46Z
New Revision: 01022af5d5a109c903e843f0e33378b5bc805ed1
URL: https://github.com/llvm/llvm-project/commit/01022af5d5a109c903e843f0e33378b5bc805ed1
DIFF: https://github.com/llvm/llvm-project/commit/01022af5d5a109c903e843f0e33378b5bc805ed1.diff
LOG: [ARM][MVE] LowOverheadLoops: DCE on the iteration count setup expression
Once we have created a tail-predicated hardware-loop, and thus know the number
of elements that are processed, we want to clean-up the iteration count
expression of that loop. In D73682, we bailed the analysis on conditionally
executed instructions. This adds support for IT-blocks, so that we can handle
these cases again. The restriction is that we only support IT blocks containing
1 statement, but that seems to cover most cases and forms of the iteration
count expression.
Differential Revision: https://reviews.llvm.org/D73947
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
Modified:
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 79896ee4c03a..7fc5e1297ae2 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -306,6 +306,7 @@ namespace {
void Expand(LowOverheadLoop &LoLoop);
+ void IterationCountDCE(LowOverheadLoop &LoLoop);
};
}
@@ -818,38 +819,100 @@ void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI, bool SkipCmp) const {
MI->eraseFromParent();
}
-MachineInstr* ARMLowOverheadLoops::ExpandLoopStart(LowOverheadLoop &LoLoop) {
- LLVM_DEBUG(dbgs() << "ARM Loops: Expanding LoopStart.\n");
- // When using tail-predication, try to delete the dead code that was used to
- // calculate the number of loop iterations.
- if (LoLoop.IsTailPredicationLegal()) {
- SmallVector<MachineInstr*, 4> Killed;
- SmallVector<MachineInstr*, 4> Dead;
- if (auto *Def = RDA->getReachingMIDef(LoLoop.Start,
- LoLoop.Start->getOperand(0).getReg())) {
- SmallPtrSet<MachineInstr*, 4> Remove;
- SmallPtrSet<MachineInstr*, 4> Ignore = { LoLoop.Start, LoLoop.Dec,
- LoLoop.End, LoLoop.InsertPt };
- SmallVector<MachineInstr*, 4> Chain = { Def };
- while (!Chain.empty()) {
- MachineInstr *MI = Chain.back();
- Chain.pop_back();
- if (TII->getPredicate(*MI) != ARMCC::AL)
- continue;
+// Perform dead code elimation on the loop iteration count setup expression.
+// If we are tail-predicating, the number of elements to be processed is the
+// operand of the VCTP instruction in the vector body, see getCount(), which is
+// register $r3 in this example:
+//
+// $lr = big-itercount-expression
+// ..
+// t2DoLoopStart renamable $lr
+// vector.body:
+// ..
+// $vpr = MVE_VCTP32 renamable $r3
+// renamable $lr = t2LoopDec killed renamable $lr, 1
+// t2LoopEnd renamable $lr, %vector.body
+// tB %end
+//
+// What we would like achieve here is to replace the do-loop start pseudo
+// instruction t2DoLoopStart with:
+//
+// $lr = MVE_DLSTP_32 killed renamable $r3
+//
+// Thus, $r3 which defines the number of elements, is written to $lr,
+// and then we want to delete the whole chain that used to define $lr,
+// see the comment below how this chain could look like.
+//
+void ARMLowOverheadLoops::IterationCountDCE(LowOverheadLoop &LoLoop) {
+ if (!LoLoop.IsTailPredicationLegal())
+ return;
- if (RDA->isSafeToRemove(MI, Remove, Ignore)) {
- for (auto &MO : MI->operands()) {
- if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
- continue;
- if (auto *Op = RDA->getReachingMIDef(MI, MO.getReg()))
- Chain.push_back(Op);
- }
- Ignore.insert(MI);
+ if (auto *Def = RDA->getReachingMIDef(LoLoop.Start,
+ LoLoop.Start->getOperand(0).getReg())) {
+ SmallPtrSet<MachineInstr*, 4> Remove;
+ SmallPtrSet<MachineInstr*, 4> Ignore = { LoLoop.Start, LoLoop.Dec,
+ LoLoop.End, LoLoop.InsertPt };
+ SmallVector<MachineInstr*, 4> Chain = { Def };
+ while (!Chain.empty()) {
+ MachineInstr *MI = Chain.back();
+ Chain.pop_back();
+
+ // If an instruction is conditionally executed, we assume here that this
+ // an IT-block with just this single instruction in it, otherwise we
+ // continue and can't perform dead-code elimination on it. This will
+ // capture most cases, because the loop iteration count expression
+ // that performs a round-up to next multiple of the vector length will
+ // look like this:
+ //
+ // %mull = ..
+ // %0 = add i32 %mul, 3
+ // %1 = icmp slt i32 %mul, 4
+ // %smin = select i1 %1, i32 %mul, i32 4
+ // %2 = sub i32 %0, %smin
+ // %3 = lshr i32 %2, 2
+ // %4 = add nuw nsw i32 %3, 1
+ //
+ // There can be a select instruction, checking if we need to execute only
+ // 1 vector iteration (in this examples that means 4 elements). Thus,
+ // we conditionally execute one instructions to materialise the iteration
+ // count.
+ MachineInstr *IT = nullptr;
+ if (TII->getPredicate(*MI) != ARMCC::AL) {
+ auto PrevMI = std::prev(MI->getIterator());
+ auto NextMI = std::next(MI->getIterator());
+
+ if (PrevMI->getOpcode() == ARM::t2IT &&
+ TII->getPredicate(*NextMI) == ARMCC::AL)
+ IT = &*PrevMI;
+ else
+ // We can't analyse IT-blocks with multiple statements. Be
+ // conservative here: clear the list, and don't remove any statements
+ // at all.
+ return;
+ }
+
+ if (RDA->isSafeToRemove(MI, Remove, Ignore)) {
+ for (auto &MO : MI->operands()) {
+ if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
+ continue;
+ if (auto *Op = RDA->getReachingMIDef(MI, MO.getReg()))
+ Chain.push_back(Op);
}
+ Ignore.insert(MI);
+
+ if (IT)
+ Remove.insert(IT);
}
- LoLoop.ToRemove.insert(Remove.begin(), Remove.end());
}
+ LoLoop.ToRemove.insert(Remove.begin(), Remove.end());
}
+}
+
+MachineInstr* ARMLowOverheadLoops::ExpandLoopStart(LowOverheadLoop &LoLoop) {
+ LLVM_DEBUG(dbgs() << "ARM Loops: Expanding LoopStart.\n");
+ // When using tail-predication, try to delete the dead code that was used to
+ // calculate the number of loop iterations.
+ IterationCountDCE(LoLoop);
MachineInstr *InsertPt = LoLoop.InsertPt;
MachineInstr *Start = LoLoop.Start;
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
index 70c20dd12432..28e409a47d12 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
@@ -100,11 +100,7 @@ body: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
- ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
- ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
- ; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
- ; CHECK: t2IT 11, 8, implicit-def $itstate
- ; CHECK: dead $r12 = t2LSLri killed renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
new file mode 100644
index 000000000000..5fcd4dee161c
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
@@ -0,0 +1,177 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+
+# IT-block with 3 statements, all chained together.
+
+--- |
+ define hidden arm_aapcs_vfpcc void @it_block_2_stmts(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
+ entry:
+ %mul = shl i32 %blockSize, 1
+ %0 = add i32 %mul, 3
+ %1 = icmp slt i32 %mul, 4
+ %smin = select i1 %1, i32 %mul, i32 4
+ %2 = sub i32 %0, %smin
+ %3 = lshr i32 %2, 2
+ %4 = add nuw nsw i32 %3, 1
+ call void @llvm.set.loop.iterations.i32(i32 %4)
+ br label %do.body
+
+ do.body: ; preds = %do.body, %entry
+ %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
+ %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
+ %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
+ %5 = phi i32 [ %4, %entry ], [ %9, %do.body ]
+ %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
+ %input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
+ %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
+ %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
+ %output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
+ tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
+ %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
+ %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
+ %sub = add nsw i32 %blkCnt.0, -4
+ %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
+ %10 = icmp ne i32 %9, 0
+ br i1 %10, label %do.body, label %do.end
+
+ do.end: ; preds = %do.body
+ ret void
+ }
+ declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
+ declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
+ declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
+ declare void @llvm.set.loop.iterations.i32(i32)
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
+
+...
+---
+name: it_block_2_stmts
+alignment: 16
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants:
+ - id: 0
+ value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
+ alignment: 16
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: it_block_2_stmts
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r2, $r7
+ ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
+ ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
+ ; CHECK: tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 11, 8, implicit-def $itstate
+ ; CHECK: $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate
+ ; CHECK: $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
+ ; CHECK: $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
+ ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
+ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
+ ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
+ ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg
+ ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK: bb.1.do.body (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
+ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
+ ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
+ ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
+ ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2.do.end:
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 16):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
+ renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
+ tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
+ t2IT 11, 8, implicit-def $itstate
+ $r1 = t2ADDri killed renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate
+ $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
+ $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
+ renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
+ renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
+ renamable $r2 = tLEApcrel %const.0, 14, $noreg
+ renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
+ t2DoLoopStart renamable $lr
+
+ bb.1.do.body (align 4):
+ successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r3
+
+ renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+ MVE_VPST 2, implicit $vpr
+ renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
+ renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
+ MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
+ renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
+ renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
+ t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
+ tB %bb.2, 14, $noreg
+
+ bb.2.do.end:
+ tPOP_RET 14, $noreg, def $r7, def $pc
+
+ bb.3 (align 16):
+ CONSTPOOL_ENTRY 0, %const.0, 16
+
+...
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
new file mode 100644
index 000000000000..10f4b58d4218
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
@@ -0,0 +1,176 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+
+# IT-block with 2 statements, which we don't support yet, so check that we do
+# not remove any of the iteration count statements.
+
+--- |
+ define hidden arm_aapcs_vfpcc void @it_block_2_stmts(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
+ entry:
+ %mul = shl i32 %blockSize, 1
+ %0 = add i32 %mul, 3
+ %1 = icmp slt i32 %mul, 4
+ %smin = select i1 %1, i32 %mul, i32 4
+ %2 = sub i32 %0, %smin
+ %3 = lshr i32 %2, 2
+ %4 = add nuw nsw i32 %3, 1
+ call void @llvm.set.loop.iterations.i32(i32 %4)
+ br label %do.body
+
+ do.body: ; preds = %do.body, %entry
+ %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
+ %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
+ %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
+ %5 = phi i32 [ %4, %entry ], [ %9, %do.body ]
+ %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
+ %input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
+ %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
+ %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
+ %output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
+ tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
+ %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
+ %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
+ %sub = add nsw i32 %blkCnt.0, -4
+ %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
+ %10 = icmp ne i32 %9, 0
+ br i1 %10, label %do.body, label %do.end
+
+ do.end: ; preds = %do.body
+ ret void
+ }
+ declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
+ declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
+ declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
+ declare void @llvm.set.loop.iterations.i32(i32)
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
+
+...
+---
+name: it_block_2_stmts
+alignment: 16
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants:
+ - id: 0
+ value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
+ alignment: 16
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: it_block_2_stmts
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
+ ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
+ ; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 11, 8, implicit-def $itstate
+ ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate
+ ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
+ ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
+ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
+ ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
+ ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg
+ ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK: bb.1.do.body (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
+ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
+ ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
+ ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
+ ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2.do.end:
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 16):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
+ renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
+ tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
+ t2IT 11, 8, implicit-def $itstate
+ $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
+ $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
+ renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
+ renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
+ renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
+ renamable $r2 = tLEApcrel %const.0, 14, $noreg
+ renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
+ t2DoLoopStart renamable $lr
+
+ bb.1.do.body (align 4):
+ successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r3
+
+ renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+ MVE_VPST 2, implicit $vpr
+ renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
+ renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
+ MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
+ renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
+ renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
+ t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
+ tB %bb.2, 14, $noreg
+
+ bb.2.do.end:
+ tPOP_RET 14, $noreg, def $r7, def $pc
+
+ bb.3 (align 16):
+ CONSTPOOL_ENTRY 0, %const.0, 16
+
+...
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
new file mode 100644
index 000000000000..128b0fe87b9b
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
@@ -0,0 +1,177 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+
+# IT-block with 2 statements, with the last instruction not connected to the
+# use-def chain of the iteration counter; make sure we don't remove the
+# IT block and any of its instructions.
+
+--- |
+ define hidden arm_aapcs_vfpcc void @it_block_2_stmts(float* %pSrc, float* %pDst, i32 %blockSize) local_unnamed_addr #0 {
+ entry:
+ %mul = shl i32 %blockSize, 1
+ %0 = add i32 %mul, 3
+ %1 = icmp slt i32 %mul, 4
+ %smin = select i1 %1, i32 %mul, i32 4
+ %2 = sub i32 %0, %smin
+ %3 = lshr i32 %2, 2
+ %4 = add nuw nsw i32 %3, 1
+ call void @llvm.set.loop.iterations.i32(i32 %4)
+ br label %do.body
+
+ do.body: ; preds = %do.body, %entry
+ %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ]
+ %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ]
+ %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
+ %5 = phi i32 [ %4, %entry ], [ %9, %do.body ]
+ %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
+ %input_cast = bitcast float* %pSrc.addr.0 to <4 x float>*
+ %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %input_cast, i32 4, <4 x i1> %6, <4 x float> undef)
+ %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>
+ %output_cast = bitcast float* %pDst.addr.0 to <4 x float>*
+ tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %8, <4 x float>* %output_cast, i32 4, <4 x i1> %6)
+ %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
+ %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4
+ %sub = add nsw i32 %blkCnt.0, -4
+ %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
+ %10 = icmp ne i32 %9, 0
+ br i1 %10, label %do.body, label %do.end
+
+ do.end: ; preds = %do.body
+ ret void
+ }
+ declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
+ declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
+ declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>)
+ declare void @llvm.set.loop.iterations.i32(i32)
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
+
+...
+---
+name: it_block_2_stmts
+alignment: 16
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants:
+ - id: 0
+ value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>'
+ alignment: 16
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: it_block_2_stmts
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
+ ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
+ ; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 11, 8, implicit-def $itstate
+ ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate
+ ; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate
+ ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
+ ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
+ ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
+ ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
+ ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg
+ ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
+ ; CHECK: bb.1.do.body (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg
+ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
+ ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg
+ ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
+ ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2.do.end:
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 16):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg
+ renamable $r12 = t2MOVi 4, 14, $noreg, $noreg
+ tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
+ t2IT 11, 8, implicit-def $itstate
+ $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
+ $r0 = t2ADDri renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate
+ renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
+ renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
+ renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
+ renamable $r2 = tLEApcrel %const.0, 14, $noreg
+ renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool)
+ t2DoLoopStart renamable $lr
+
+ bb.1.do.body (align 4):
+ successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r3
+
+ renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+ MVE_VPST 2, implicit $vpr
+ renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr
+ renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1
+ MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr
+ renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
+ renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
+ t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
+ tB %bb.2, 14, $noreg
+
+ bb.2.do.end:
+ tPOP_RET 14, $noreg, def $r7, def $pc
+
+ bb.3 (align 16):
+ CONSTPOOL_ENTRY 0, %const.0, 16
+
+...
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