[llvm] a328536 - [ARM] Correct syntax of the CLRM insn
Momchil Velikov via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 5 05:55:37 PST 2020
Author: Momchil Velikov
Date: 2020-02-05T13:54:34Z
New Revision: a328536c6d7ac16946c5b01fffa16dadb80b0d29
URL: https://github.com/llvm/llvm-project/commit/a328536c6d7ac16946c5b01fffa16dadb80b0d29
DIFF: https://github.com/llvm/llvm-project/commit/a328536c6d7ac16946c5b01fffa16dadb80b0d29.diff
LOG: [ARM] Correct syntax of the CLRM insn
The predicate should be adjacent to the opcode.
Differential Revision: https://reviews.llvm.org/D74040
Added:
Modified:
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/MC/Disassembler/ARM/clrm.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 8c6f187b8b12..1c5764e20d2e 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -5207,7 +5207,7 @@ class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm,
def t2CLRM : V8_1MI<(outs),
(ins pred:$p, reglist_with_apsr:$regs, variable_ops),
- AddrModeNone, NoItinerary, "clrm", "${p}\t$regs", "", []> {
+ AddrModeNone, NoItinerary, "clrm${p}", "$regs", "", []> {
bits<16> regs;
let Inst{31-16} = 0b1110100010011111;
diff --git a/llvm/test/MC/Disassembler/ARM/clrm.txt b/llvm/test/MC/Disassembler/ARM/clrm.txt
index 6062e14bae0e..d182d6832c34 100644
--- a/llvm/test/MC/Disassembler/ARM/clrm.txt
+++ b/llvm/test/MC/Disassembler/ARM/clrm.txt
@@ -16,5 +16,10 @@
[0x9f,0xe8,0x00,0x80]
# CHECK: clrm {apsr} @ encoding: [0x9f,0xe8,0x00,0x80]
+[0x04,0xbf]
+[0x9f,0xe8,0x0f,0x00]
+# CHECK: itt eq
+# CHECK: clrmeq {r0, r1, r2, r3}
+
[0x9f,0xe8,0x00,0x00]
# ERROR: [[@LINE-1]]:2: warning: invalid instruction encoding
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