[PATCH] D73953: [AArch64] Predictably disassemble system registers with the same encoding

[Momchil Velikov via Phabricator via llvm-commits]

chill added a comment.

In D73953#1858998 <https://reviews.llvm.org/D73953#1858998>, @sdesmalen wrote:

> we probably shouldn't rely on the order of definitions in the TableGen file to get the output we expect.


The unnamed TableGen records get a name like `annonymous_NNN...NN` where `NNN...NN`
are monotonically increasing numbers, assigned in the order of definitions. The lexicographic order of the names
does not correspond to the numerical order. We are not relying on the order of definitions, but on the order
of explicitly spelled names.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73953/new/

https://reviews.llvm.org/D73953