[PATCH] D73984: [NFC][RISCV] Fixing typo in comment.
Nate Voorhies via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 4 11:35:44 PST 2020
ncv created this revision.
Herald added subscribers: llvm-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.
ncv added a reviewer: luismarques.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D73984
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -90,7 +90,7 @@
}
// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
-// relocation types. We those pseudo-instructions while encoding them, meaning
+// relocation types. We expand pseudo-instructions while encoding them, meaning
// AUIPC and JALR won't go through RISCV MC to MC compressed instruction
// transformation. This is acceptable because AUIPC has no 16-bit form and
// C_JALR have no immediate operand field. We let linker relaxation deal with
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