[llvm] 163e33b - [AMDGPU] Fix lowering a16 image intrinsics
Sebastian Neubauer via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 5 01:55:34 PST 2020
Author: Sebastian Neubauer
Date: 2020-02-05T10:54:34+01:00
New Revision: 163e33b290ff4b3bc3eec569a153ced9267254ec
URL: https://github.com/llvm/llvm-project/commit/163e33b290ff4b3bc3eec569a153ced9267254ec
DIFF: https://github.com/llvm/llvm-project/commit/163e33b290ff4b3bc3eec569a153ced9267254ec.diff
LOG: [AMDGPU] Fix lowering a16 image intrinsics
scalar_to_vector takes only one argument, not two.
The a16 tests now also check the packing of coordinates into registers
Differential Revision: https://reviews.llvm.org/D73482
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 935e98f36241..ec347cc2eae6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5407,26 +5407,27 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
IsA16 = true;
const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {
- SDValue AddrLo, AddrHi;
+ SDValue AddrLo;
// Push back extra arguments.
if (i < DimIdx) {
AddrLo = Op.getOperand(i);
} else {
- AddrLo = Op.getOperand(i);
// Dz/dh, dz/dv and the last odd coord are packed with undef. Also,
// in 1D, derivatives dx/dh and dx/dv are packed with undef.
if (((i + 1) >= (AddrIdx + NumMIVAddrs)) ||
((NumGradients / 2) % 2 == 1 &&
(i == DimIdx + (NumGradients / 2) - 1 ||
i == DimIdx + NumGradients - 1))) {
- AddrHi = DAG.getUNDEF(MVT::f16);
+ AddrLo = Op.getOperand(i);
+ if (AddrLo.getValueType() != MVT::i16)
+ AddrLo = DAG.getBitcast(MVT::i16, Op.getOperand(i));
+ AddrLo = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, AddrLo);
} else {
- AddrHi = Op.getOperand(i + 1);
+ AddrLo = DAG.getBuildVector(VectorVT, DL,
+ {Op.getOperand(i), Op.getOperand(i + 1)});
i++;
}
- AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
- {AddrLo, AddrHi});
- AddrLo = DAG.getBitcast(MVT::i32, AddrLo);
+ AddrLo = DAG.getBitcast(MVT::f32, AddrLo);
}
VAddrs.push_back(AddrLo);
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
index 89b23c7742cb..bc3b01a0f062 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
@@ -1,112 +1,222 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
-; GCN-LABEL: {{^}}gather4_2d:
-; GCN: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
+; GCN-LABEL: gather4_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_cube:
-; GCN: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16 da{{$}}
define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {
+; GCN-LABEL: gather4_cube:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4 v[0:3], v[1:2], s[0:7], s[8:11] dmask:0x1 a16 da
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.cube.v4f32.f16(i32 1, half %s, half %t, half %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_2darray:
-; GCN: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16 da{{$}}
define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {
+; GCN-LABEL: gather4_2darray:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4 v[0:3], v[1:2], s[0:7], s[8:11] dmask:0x1 a16 da
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.2darray.v4f32.f16(i32 1, half %s, half %t, half %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_c_2d:
-; GCN: image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
+; GCN-LABEL: gather4_c_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_cl_2d:
-; GCN: image_gather4_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {
+; GCN-LABEL: gather4_cl_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_cl v[0:3], v[1:2], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f16(i32 1, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_c_cl_2d:
-; GCN: image_gather4_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {
+; GCN-LABEL: gather4_c_cl_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_mov_b32_e32 v5, v3
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v4, v2, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_c_cl v[0:3], v[3:5], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_b_2d:
-; GCN: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t) {
+; GCN-LABEL: gather4_b_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.f16(i32 1, float %bias, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_c_b_2d:
-; GCN: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t) {
+; GCN-LABEL: gather4_c_b_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.f16(i32 1, float %bias, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_b_cl_2d:
-; GCN: image_gather4_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {
+; GCN-LABEL: gather4_b_cl_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_mov_b32_e32 v5, v3
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v4, v2, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_b_cl v[0:3], v[3:5], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.2d.v4f32.f32.f16(i32 1, float %bias, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_c_b_cl_2d:
-; GCN: image_gather4_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t, half %clamp) {
+; GCN-LABEL: gather4_c_b_cl_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: s_mov_b64 s[12:13], exec
+; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_mov_b32_e32 v7, v4
+; GCN-NEXT: v_mov_b32_e32 v4, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; GCN-NEXT: v_mov_b32_e32 v5, v1
+; GCN-NEXT: v_lshl_or_b32 v6, v3, 16, v0
+; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
+; GCN-NEXT: image_gather4_c_b_cl v[0:3], v[4:7], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f16(i32 1, float %bias, float %zcompare, half %s, half %t, half %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_l_2d:
-; GCN: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {
+; GCN-LABEL: gather4_l_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
+; GCN-NEXT: image_gather4_l v[0:3], v[1:2], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f16(i32 1, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_c_l_2d:
-; GCN: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {
+; GCN-LABEL: gather4_c_l_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_mov_b32_e32 v5, v3
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v4, v2, 16, v0
+; GCN-NEXT: image_gather4_c_l v[0:3], v[3:5], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, half %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_lz_2d:
-; GCN: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
+; GCN-LABEL: gather4_lz_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GCN-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
}
-; GCN-LABEL: {{^}}gather4_c_lz_2d:
-; GCN: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16{{$}}
define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
+; GCN-LABEL: gather4_c_lz_2d:
+; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GCN-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 a16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: ; return to shader part epilog
main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32(i32 1, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
ret <4 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
index 48a3690ce7da..2b6435647554 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
@@ -19,6 +19,8 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -33,9 +35,10 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -48,9 +51,10 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16 da
+; GCN-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf a16 da
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -63,6 +67,8 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16 da
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -77,9 +83,10 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16 da
+; GCN-NEXT: image_sample v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf a16 da
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -106,6 +113,8 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -120,6 +129,8 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_cl v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -134,9 +145,10 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: image_sample_cl v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -149,6 +161,8 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_c_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -163,9 +177,12 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v2, v3
+; GCN-NEXT: v_mov_b32_e32 v5, v3
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v4, v2, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: image_sample_c_cl v[0:3], v[3:5], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -192,6 +209,8 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -220,6 +239,8 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -234,6 +255,8 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_b_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -248,9 +271,12 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v2, v3
+; GCN-NEXT: v_mov_b32_e32 v5, v3
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v4, v2, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: image_sample_b_cl v[0:3], v[3:5], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -263,6 +289,8 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
; GCN-NEXT: image_sample_c_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
@@ -277,9 +305,13 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b64 s[12:13], exec
; GCN-NEXT: s_wqm_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v3, v4
+; GCN-NEXT: v_mov_b32_e32 v7, v4
+; GCN-NEXT: v_mov_b32_e32 v4, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; GCN-NEXT: v_mov_b32_e32 v5, v1
+; GCN-NEXT: v_lshl_or_b32 v6, v3, 16, v0
; GCN-NEXT: s_and_b64 exec, exec, s[12:13]
-; GCN-NEXT: image_sample_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: image_sample_c_b_cl v[0:3], v[4:7], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -301,9 +333,14 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GCN-LABEL: sample_d_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v3, v4
-; GCN-NEXT: v_mov_b32_e32 v1, v0
-; GCN-NEXT: image_sample_d v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v6, 0xffff
+; GCN-NEXT: v_and_b32_e32 v4, v6, v4
+; GCN-NEXT: v_and_b32_e32 v2, v6, v2
+; GCN-NEXT: v_and_b32_e32 v0, v6, v0
+; GCN-NEXT: v_lshl_or_b32 v3, v3, 16, v2
+; GCN-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GCN-NEXT: v_lshl_or_b32 v2, v1, 16, v0
+; GCN-NEXT: image_sample_d v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -314,11 +351,17 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r) {
; GCN-LABEL: sample_d_3d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v4, v3
-; GCN-NEXT: v_mov_b32_e32 v3, v2
-; GCN-NEXT: v_mov_b32_e32 v7, v8
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_d v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v12, v8
+; GCN-NEXT: v_mov_b32_e32 v8, v2
+; GCN-NEXT: v_mov_b32_e32 v2, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v10, v5
+; GCN-NEXT: v_and_b32_e32 v5, v2, v6
+; GCN-NEXT: v_and_b32_e32 v3, v2, v3
+; GCN-NEXT: v_and_b32_e32 v0, v2, v0
+; GCN-NEXT: v_lshl_or_b32 v11, v7, 16, v5
+; GCN-NEXT: v_lshl_or_b32 v9, v4, 16, v3
+; GCN-NEXT: v_lshl_or_b32 v7, v1, 16, v0
+; GCN-NEXT: image_sample_d v[0:3], v[7:14], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -340,10 +383,16 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GCN-LABEL: sample_c_d_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v2, v1
-; GCN-NEXT: v_mov_b32_e32 v4, v5
-; GCN-NEXT: v_mov_b32_e32 v1, v0
-; GCN-NEXT: image_sample_c_d v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v9, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v8, v2
+; GCN-NEXT: v_mov_b32_e32 v7, v3
+; GCN-NEXT: v_and_b32_e32 v2, v9, v5
+; GCN-NEXT: v_and_b32_e32 v1, v9, v1
+; GCN-NEXT: v_lshl_or_b32 v3, v6, 16, v2
+; GCN-NEXT: v_and_b32_e32 v2, v9, v7
+; GCN-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GCN-NEXT: v_lshl_or_b32 v1, v8, 16, v1
+; GCN-NEXT: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -354,6 +403,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {
; GCN-LABEL: sample_d_cl_1d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GCN-NEXT: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -365,10 +416,14 @@ main_body:
define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
; GCN-LABEL: sample_d_cl_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v3, v2
-; GCN-NEXT: v_mov_b32_e32 v5, v6
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_d_cl v[0:3], v[2:5], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v7, 0xffff
+; GCN-NEXT: v_and_b32_e32 v4, v7, v4
+; GCN-NEXT: v_and_b32_e32 v2, v7, v2
+; GCN-NEXT: v_and_b32_e32 v0, v7, v0
+; GCN-NEXT: v_lshl_or_b32 v5, v5, 16, v4
+; GCN-NEXT: v_lshl_or_b32 v4, v3, 16, v2
+; GCN-NEXT: v_lshl_or_b32 v3, v1, 16, v0
+; GCN-NEXT: image_sample_d_cl v[0:3], v[3:6], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -379,6 +434,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {
; GCN-LABEL: sample_c_d_cl_1d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GCN-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GCN-NEXT: image_sample_c_d_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -390,11 +447,16 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
; GCN-LABEL: sample_c_d_cl_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v4, v3
-; GCN-NEXT: v_mov_b32_e32 v6, v7
-; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_c_d_cl v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v11, v7
+; GCN-NEXT: v_mov_b32_e32 v7, v0
+; GCN-NEXT: v_mov_b32_e32 v0, 0xffff
+; GCN-NEXT: v_and_b32_e32 v5, v0, v5
+; GCN-NEXT: v_and_b32_e32 v3, v0, v3
+; GCN-NEXT: v_and_b32_e32 v0, v0, v1
+; GCN-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GCN-NEXT: v_lshl_or_b32 v9, v4, 16, v3
+; GCN-NEXT: v_lshl_or_b32 v8, v2, 16, v0
+; GCN-NEXT: image_sample_c_d_cl v[0:3], v[7:14], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -416,9 +478,14 @@ main_body:
define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GCN-LABEL: sample_cd_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v3, v4
-; GCN-NEXT: v_mov_b32_e32 v1, v0
-; GCN-NEXT: image_sample_cd v[0:3], v[1:3], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v6, 0xffff
+; GCN-NEXT: v_and_b32_e32 v4, v6, v4
+; GCN-NEXT: v_and_b32_e32 v2, v6, v2
+; GCN-NEXT: v_and_b32_e32 v0, v6, v0
+; GCN-NEXT: v_lshl_or_b32 v3, v3, 16, v2
+; GCN-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GCN-NEXT: v_lshl_or_b32 v2, v1, 16, v0
+; GCN-NEXT: image_sample_cd v[0:3], v[2:4], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -440,10 +507,16 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {
; GCN-LABEL: sample_c_cd_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v2, v1
-; GCN-NEXT: v_mov_b32_e32 v4, v5
-; GCN-NEXT: v_mov_b32_e32 v1, v0
-; GCN-NEXT: image_sample_c_cd v[0:3], v[1:4], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v9, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v8, v2
+; GCN-NEXT: v_mov_b32_e32 v7, v3
+; GCN-NEXT: v_and_b32_e32 v2, v9, v5
+; GCN-NEXT: v_and_b32_e32 v1, v9, v1
+; GCN-NEXT: v_lshl_or_b32 v3, v6, 16, v2
+; GCN-NEXT: v_and_b32_e32 v2, v9, v7
+; GCN-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GCN-NEXT: v_lshl_or_b32 v1, v8, 16, v1
+; GCN-NEXT: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -454,6 +527,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {
; GCN-LABEL: sample_cd_cl_1d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GCN-NEXT: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -465,10 +540,14 @@ main_body:
define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
; GCN-LABEL: sample_cd_cl_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v3, v2
-; GCN-NEXT: v_mov_b32_e32 v5, v6
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_cd_cl v[0:3], v[2:5], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v7, 0xffff
+; GCN-NEXT: v_and_b32_e32 v4, v7, v4
+; GCN-NEXT: v_and_b32_e32 v2, v7, v2
+; GCN-NEXT: v_and_b32_e32 v0, v7, v0
+; GCN-NEXT: v_lshl_or_b32 v5, v5, 16, v4
+; GCN-NEXT: v_lshl_or_b32 v4, v3, 16, v2
+; GCN-NEXT: v_lshl_or_b32 v3, v1, 16, v0
+; GCN-NEXT: image_sample_cd_cl v[0:3], v[3:6], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -479,6 +558,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {
; GCN-LABEL: sample_c_cd_cl_1d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GCN-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GCN-NEXT: image_sample_c_cd_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -490,11 +571,16 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {
; GCN-LABEL: sample_c_cd_cl_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v4, v3
-; GCN-NEXT: v_mov_b32_e32 v6, v7
-; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_c_cd_cl v[0:3], v[2:9], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v11, v7
+; GCN-NEXT: v_mov_b32_e32 v7, v0
+; GCN-NEXT: v_mov_b32_e32 v0, 0xffff
+; GCN-NEXT: v_and_b32_e32 v5, v0, v5
+; GCN-NEXT: v_and_b32_e32 v3, v0, v3
+; GCN-NEXT: v_and_b32_e32 v0, v0, v1
+; GCN-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GCN-NEXT: v_lshl_or_b32 v9, v4, 16, v3
+; GCN-NEXT: v_lshl_or_b32 v8, v2, 16, v0
+; GCN-NEXT: image_sample_c_cd_cl v[0:3], v[7:14], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -505,6 +591,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %lod) {
; GCN-LABEL: sample_l_1d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GCN-NEXT: image_sample_l v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -516,8 +604,9 @@ main_body:
define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {
; GCN-LABEL: sample_l_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v1, v2
-; GCN-NEXT: image_sample_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v0
+; GCN-NEXT: image_sample_l v[0:3], v[1:2], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -528,6 +617,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %lod) {
; GCN-LABEL: sample_c_l_1d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GCN-NEXT: image_sample_c_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -539,8 +630,11 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {
; GCN-LABEL: sample_c_l_2d:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v2, v3
-; GCN-NEXT: image_sample_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf a16
+; GCN-NEXT: v_mov_b32_e32 v5, v3
+; GCN-NEXT: v_mov_b32_e32 v3, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v4, v2, 16, v0
+; GCN-NEXT: image_sample_c_l v[0:3], v[3:5], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -562,6 +656,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
; GCN-LABEL: sample_lz_2d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GCN-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -584,6 +680,8 @@ main_body:
define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {
; GCN-LABEL: sample_c_lz_2d:
; GCN: ; %bb.0: ; %main_body
+; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GCN-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GCN-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf a16
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
@@ -595,12 +693,17 @@ main_body:
define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {
; GCN-LABEL: sample_c_d_o_2darray_V1:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v5, v4
-; GCN-NEXT: v_mov_b32_e32 v4, v2
-; GCN-NEXT: v_mov_b32_e32 v7, v8
-; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_c_d_o v0, v[2:9], s[0:7], s[8:11] dmask:0x4 a16 da
+; GCN-NEXT: v_mov_b32_e32 v13, v8
+; GCN-NEXT: v_mov_b32_e32 v8, v0
+; GCN-NEXT: v_mov_b32_e32 v0, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v9, v1
+; GCN-NEXT: v_and_b32_e32 v1, v0, v6
+; GCN-NEXT: v_lshl_or_b32 v12, v7, 16, v1
+; GCN-NEXT: v_and_b32_e32 v1, v0, v4
+; GCN-NEXT: v_and_b32_e32 v0, v0, v2
+; GCN-NEXT: v_lshl_or_b32 v11, v5, 16, v1
+; GCN-NEXT: v_lshl_or_b32 v10, v3, 16, v0
+; GCN-NEXT: image_sample_c_d_o v0, v[8:15], s[0:7], s[8:11] dmask:0x4 a16 da
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
@@ -611,12 +714,17 @@ main_body:
define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {
; GCN-LABEL: sample_c_d_o_2darray_V2:
; GCN: ; %bb.0: ; %main_body
-; GCN-NEXT: v_mov_b32_e32 v5, v4
-; GCN-NEXT: v_mov_b32_e32 v4, v2
-; GCN-NEXT: v_mov_b32_e32 v7, v8
-; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_mov_b32_e32 v2, v0
-; GCN-NEXT: image_sample_c_d_o v[0:1], v[2:9], s[0:7], s[8:11] dmask:0x6 a16 da
+; GCN-NEXT: v_mov_b32_e32 v13, v8
+; GCN-NEXT: v_mov_b32_e32 v8, v0
+; GCN-NEXT: v_mov_b32_e32 v0, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v9, v1
+; GCN-NEXT: v_and_b32_e32 v1, v0, v6
+; GCN-NEXT: v_lshl_or_b32 v12, v7, 16, v1
+; GCN-NEXT: v_and_b32_e32 v1, v0, v4
+; GCN-NEXT: v_and_b32_e32 v0, v0, v2
+; GCN-NEXT: v_lshl_or_b32 v11, v5, 16, v1
+; GCN-NEXT: v_lshl_or_b32 v10, v3, 16, v0
+; GCN-NEXT: image_sample_c_d_o v[0:1], v[8:15], s[0:7], s[8:11] dmask:0x6 a16 da
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
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