[llvm] 9b0ce8e - AMDGPU/GlobalISel: Remove extension legality hacks

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 4 12:50:59 PST 2020


Author: Matt Arsenault
Date: 2020-02-04T12:50:47-08:00
New Revision: 9b0ce8edfaff513350b4fd55911fe43192073c24

URL: https://github.com/llvm/llvm-project/commit/9b0ce8edfaff513350b4fd55911fe43192073c24
DIFF: https://github.com/llvm/llvm-project/commit/9b0ce8edfaff513350b4fd55911fe43192073c24.diff

LOG: AMDGPU/GlobalISel: Remove extension legality hacks

The legalization has improved since this was added, and the tests
relying on this no longer need it.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 1ad62aa81e53..c5392dee4a8b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -174,7 +174,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   };
 
   const LLT S1 = LLT::scalar(1);
-  const LLT S8 = LLT::scalar(8);
   const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
@@ -439,11 +438,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
 
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
     .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
-               {S32, S1}, {S64, S1}, {S16, S1},
-               {S96, S32},
-               // FIXME: Hack
-               {S64, LLT::scalar(33)},
-               {S32, S8}, {S32, LLT::scalar(24)}})
+               {S32, S1}, {S64, S1}, {S16, S1}})
     .scalarize(0)
     .clampScalar(0, S32, S64);
 

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
index 0c91352ba1c6..58d01774f745 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
@@ -4,25 +4,6 @@
 
 ---
 
-name: anyext_sgpr_s8_to_sgpr_s32
-legalized:       true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; GCN-LABEL: name: anyext_sgpr_s8_to_sgpr_s32
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GCN: $sgpr0 = COPY [[COPY]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s8) = G_TRUNC %0
-    %2:sgpr(s32) = G_ANYEXT %1
-    $sgpr0 = COPY %2
-
-...
-
----
-
 name: anyext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
@@ -132,25 +113,6 @@ body: |
 
 ---
 
-name: anyext_vgpr_s8_to_vgpr_s32
-legalized:       true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; GCN-LABEL: name: anyext_vgpr_s8_to_vgpr_s32
-    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: $vgpr0 = COPY [[COPY]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s8) = G_TRUNC %0
-    %2:vgpr(s32) = G_ANYEXT %1
-    $vgpr0 = COPY %2
-
-...
-
----
-
 name: anyext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
index d25a74ce1ab1..1f1169d0f1c6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
@@ -43,25 +43,6 @@ body: |
 
 ---
 
-name: sext_sgpr_s8_to_sgpr_s32
-legalized:       true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; GCN-LABEL: name: sext_sgpr_s8_to_sgpr_s32
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GCN: [[S_SEXT_I32_I8_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I8 [[COPY]]
-    ; GCN: $sgpr0 = COPY [[S_SEXT_I32_I8_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s8) = G_TRUNC %0
-    %2:sgpr(s32) = G_SEXT %1
-    $sgpr0 = COPY %2
-...
-
----
-
 name: sext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
@@ -138,26 +119,6 @@ body: |
 
 ---
 
-name: sext_vgpr_s8_to_vgpr_s32
-legalized:       true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; GCN-LABEL: name: sext_vgpr_s8_to_vgpr_s32
-    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[V_BFE_I32_:%[0-9]+]]:vgpr_32 = V_BFE_I32 [[COPY]], 0, 8, implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_BFE_I32_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s8) = G_TRUNC %0
-    %2:vgpr(s32) = G_SEXT %1
-    $vgpr0 = COPY %2
-
-...
-
----
-
 name: sext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
index 0ae30e3e54ba..e89461d4ce5d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
@@ -43,26 +43,6 @@ body: |
 
 ---
 
-name: zext_sgpr_s8_to_sgpr_s32
-legalized:       true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $sgpr0
-
-    ; GCN-LABEL: name: zext_sgpr_s8_to_sgpr_s32
-    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 524288, implicit-def $scc
-    ; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
-    %0:sgpr(s32) = COPY $sgpr0
-    %1:sgpr(s8) = G_TRUNC %0
-    %2:sgpr(s32) = G_ZEXT %1
-    $sgpr0 = COPY %2
-
-...
-
----
-
 name: zext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
@@ -139,26 +119,6 @@ body: |
 
 ---
 
-name: zext_vgpr_s8_to_vgpr_s32
-legalized:       true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $vgpr0
-
-    ; GCN-LABEL: name: zext_vgpr_s8_to_vgpr_s32
-    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GCN: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[COPY]], 0, 8, implicit $exec
-    ; GCN: $vgpr0 = COPY [[V_BFE_U32_]]
-    %0:vgpr(s32) = COPY $vgpr0
-    %1:vgpr(s8) = G_TRUNC %0
-    %2:vgpr(s32) = G_ZEXT %1
-    $vgpr0 = COPY %2
-
-...
-
----
-
 name: zext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
index 745a794cf97d..15c6d3ff4ffd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -274,6 +274,25 @@ body: |
     S_ENDPGM 0, implicit %2
 ...
 
+---
+name: test_anyext_s32_to_s96
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_anyext_s32_to_s96
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
+    ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
+    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s96)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s96) = G_ANYEXT %0
+    S_ENDPGM 0, implicit %1
+...
+
 ---
 name: test_anyext_s32_to_s128
 body: |

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
index 0c5fe5de2851..6bf18fb1c4a5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
@@ -291,22 +291,26 @@ body: |
 
     ; CHECK-LABEL: name: test_bitcast_s24_to_v3s8
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s96) = G_ANYEXT [[COPY]](s32)
-    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s96)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
+    ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[TRUNC]](s32)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
     ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
-    ; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
-    ; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
-    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
-    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
+    ; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     %0:_(s32) = COPY $vgpr0
     %1:_(s24) = G_TRUNC %0

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
index ed07890b5122..927273d83339 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -328,6 +328,26 @@ body: |
     S_ENDPGM 0, implicit %2
 ...
 
+---
+name: test_sext_s32_to_s96
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_sext_s32_to_s96
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
+    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
+    ; CHECK: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192)
+    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s96)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s96) = G_SEXT %0
+    S_ENDPGM 0, implicit %1
+...
+
 ---
 name: test_sext_s32_to_s128
 body: |

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index a3aa3e88677a..18af29f00f3f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -70,6 +70,25 @@ body: |
     $vgpr0 = COPY %2
 ...
 
+---
+name: test_zext_s32_to_s96
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_zext_s32_to_s96
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
+    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[TRUNC]](s96)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s96) = G_ZEXT %0
+    $vgpr0_vgpr1_vgpr2 = COPY %1
+...
+
 ---
 name: test_zext_i1_to_s32
 body: |


        


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