[llvm] b8dc54c - PowerPC: Remove redundancy in ternary for predicate selection
Justin Hibbits via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 4 08:40:32 PST 2020
Author: Justin Hibbits
Date: 2020-02-04T10:38:21-06:00
New Revision: b8dc54cf39b41252f31154079a834aa83e9892d8
URL: https://github.com/llvm/llvm-project/commit/b8dc54cf39b41252f31154079a834aa83e9892d8
DIFF: https://github.com/llvm/llvm-project/commit/b8dc54cf39b41252f31154079a834aa83e9892d8.diff
LOG: PowerPC: Remove redundancy in ternary for predicate selection
rG2c4620ad57b8 inadvertently added redundancies in selection of GT and
LE predicates for SPE. Correct this.
Partially addresses PR 44768.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index b1c33a33568d..d69fdf75b82f 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3872,10 +3872,10 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC, const EVT &VT,
return UseSPE ? PPC::PRED_GT : PPC::PRED_LT;
case ISD::SETULE:
case ISD::SETLE:
- return UseSPE ? PPC::PRED_LE : PPC::PRED_LE;
+ return PPC::PRED_LE;
case ISD::SETOGT:
case ISD::SETGT:
- return UseSPE ? PPC::PRED_GT : PPC::PRED_GT;
+ return PPC::PRED_GT;
case ISD::SETUGE:
case ISD::SETGE:
return UseSPE ? PPC::PRED_LE : PPC::PRED_GE;
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