[PATCH] D73953: [AArch64] Predictably disassemble system registers with the same encoding

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added a comment.

We already have a hack for a similar problem in `AArch64InstPrinter::printMRSSystemRegister` and `AArch64InstPrinter::printMSRSystemRegister`, I think it would be better to do this there to keep all of the related hacks together. This avoids relying on the sorting order of the table (which isn't obvious that it needs to be preserved), and will make it more obvious once we have enough of these hacks to be worth improving the tablegen backend to handle them.

If you still think it's better to do it here, please add comments both here (explaining why these names are significant) and in tablegen (explaining that we rely on sorting by name).


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  https://reviews.llvm.org/D73953/new/

https://reviews.llvm.org/D73953