[PATCH] D73867: [AMDGPU] getMemOperandsWithOffset: add resource operand for BUF instructions
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 3 09:10:22 PST 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rG05297b7cbe9b: [AMDGPU] getMemOperandsWithOffset: add resource operand for BUF instructions (authored by foad).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D73867/new/
https://reviews.llvm.org/D73867
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/smrd.ll
Index: llvm/test/CodeGen/AMDGPU/smrd.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/smrd.ll
+++ llvm/test/CodeGen/AMDGPU/smrd.ll
@@ -482,8 +482,8 @@
; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting)
; GCN-LABEL: {{^}}smrd_load_nonconst2:
-; SIVIGFX9_10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
-; SIVIGFX9_10: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
+; SIVIGFX9_10-DAG: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
+; SIVIGFX9_10-DAG: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; CI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; GCN: s_endpgm
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -331,26 +331,24 @@
const MachineOperand *OffsetImm =
getNamedOperand(LdSt, AMDGPU::OpName::offset);
+ BaseOps.push_back(RSrc);
BaseOps.push_back(SOffset);
Offset = OffsetImm->getImm();
return true;
}
- const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
- if (!AddrReg)
+ BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
+ if (!BaseOp)
return false;
+ const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
+ BaseOps.push_back(RSrc);
+ BaseOps.push_back(BaseOp);
const MachineOperand *OffsetImm =
getNamedOperand(LdSt, AMDGPU::OpName::offset);
- BaseOp = AddrReg;
Offset = OffsetImm->getImm();
if (SOffset) // soffset can be an inline immediate.
Offset += SOffset->getImm();
-
- if (!BaseOp->isReg())
- return false;
-
- BaseOps.push_back(BaseOp);
return true;
}
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