[llvm] 5c2e620 - [InstCombine] regenerate complete test checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 3 07:30:35 PST 2020
Author: Sanjay Patel
Date: 2020-02-03T10:30:26-05:00
New Revision: 5c2e6207b7c3b3edc59e4b6ffe73d4b231908ff7
URL: https://github.com/llvm/llvm-project/commit/5c2e6207b7c3b3edc59e4b6ffe73d4b231908ff7
DIFF: https://github.com/llvm/llvm-project/commit/5c2e6207b7c3b3edc59e4b6ffe73d4b231908ff7.diff
LOG: [InstCombine] regenerate complete test checks; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/cast_phi.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/cast_phi.ll b/llvm/test/Transforms/InstCombine/cast_phi.ll
index 141ad186002d..0589adde4813 100644
--- a/llvm/test/Transforms/InstCombine/cast_phi.ll
+++ b/llvm/test/Transforms/InstCombine/cast_phi.ll
@@ -1,9 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
define void @MainKernel(i32 %iNumSteps, i32 %tid, i32 %base) {
-; CHECK-NOT: bitcast
-
+; CHECK-LABEL: @MainKernel(
+; CHECK-NEXT: [[CALLA:%.*]] = alloca [258 x float], align 4
+; CHECK-NEXT: [[CALLB:%.*]] = alloca [258 x float], align 4
+; CHECK-NEXT: [[CONV_I:%.*]] = uitofp i32 [[INUMSTEPS:%.*]] to float
+; CHECK-NEXT: [[CONV_I12:%.*]] = zext i32 [[TID:%.*]] to i64
+; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [258 x float], [258 x float]* [[CALLA]], i64 0, i64 [[CONV_I12]]
+; CHECK-NEXT: store float [[CONV_I]], float* [[ARRAYIDX3]], align 4
+; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [258 x float], [258 x float]* [[CALLB]], i64 0, i64 [[CONV_I12]]
+; CHECK-NEXT: store float [[CONV_I]], float* [[ARRAYIDX6]], align 4
+; CHECK-NEXT: [[CMP7:%.*]] = icmp eq i32 [[TID]], 0
+; CHECK-NEXT: br i1 [[CMP7]], label [[DOTBB1:%.*]], label [[DOTBB2:%.*]]
+; CHECK: .bb1:
+; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [258 x float], [258 x float]* [[CALLA]], i64 0, i64 256
+; CHECK-NEXT: store float [[CONV_I]], float* [[ARRAYIDX10]], align 4
+; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [258 x float], [258 x float]* [[CALLB]], i64 0, i64 256
+; CHECK-NEXT: store float 0.000000e+00, float* [[ARRAYIDX11]], align 4
+; CHECK-NEXT: br label [[DOTBB2]]
+; CHECK: .bb2:
+; CHECK-NEXT: [[CMP135:%.*]] = icmp sgt i32 [[INUMSTEPS]], 0
+; CHECK-NEXT: br i1 [[CMP135]], label [[DOTBB3:%.*]], label [[DOTBB8:%.*]]
+; CHECK: .bb3:
+; CHECK-NEXT: [[TMP1:%.*]] = phi float [ [[TMP10:%.*]], [[DOTBB12:%.*]] ], [ [[CONV_I]], [[DOTBB2]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = phi float [ [[TMP11:%.*]], [[DOTBB12]] ], [ [[CONV_I]], [[DOTBB2]] ]
+; CHECK-NEXT: [[I12_06:%.*]] = phi i32 [ [[SUB:%.*]], [[DOTBB12]] ], [ [[INUMSTEPS]], [[DOTBB2]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[I12_06]], [[BASE:%.*]]
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I12_06]], 1
+; CHECK-NEXT: [[CONV_I9:%.*]] = sext i32 [[ADD]] to i64
+; CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [258 x float], [258 x float]* [[CALLA]], i64 0, i64 [[CONV_I9]]
+; CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [258 x float], [258 x float]* [[CALLB]], i64 0, i64 [[CONV_I9]]
+; CHECK-NEXT: [[CMP40:%.*]] = icmp ult i32 [[I12_06]], [[BASE]]
+; CHECK-NEXT: br i1 [[TMP3]], label [[DOTBB4:%.*]], label [[DOTBB5:%.*]]
+; CHECK: .bb4:
+; CHECK-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX20]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX24]], align 4
+; CHECK-NEXT: [[ADD33:%.*]] = fadd float [[TMP5]], [[TMP4]]
+; CHECK-NEXT: [[ADD33_1:%.*]] = fadd float [[ADD33]], [[TMP1]]
+; CHECK-NEXT: [[ADD33_2:%.*]] = fadd float [[ADD33_1]], [[TMP2]]
+; CHECK-NEXT: br label [[DOTBB5]]
+; CHECK: .bb5:
+; CHECK-NEXT: [[TMP6:%.*]] = phi float [ [[ADD33_1]], [[DOTBB4]] ], [ [[TMP1]], [[DOTBB3]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = phi float [ [[ADD33_2]], [[DOTBB4]] ], [ [[TMP2]], [[DOTBB3]] ]
+; CHECK-NEXT: br i1 [[CMP40]], label [[DOTBB6:%.*]], label [[DOTBB7:%.*]]
+; CHECK: .bb6:
+; CHECK-NEXT: store float [[TMP7]], float* [[ARRAYIDX3]], align 4
+; CHECK-NEXT: store float [[TMP6]], float* [[ARRAYIDX6]], align 4
+; CHECK-NEXT: br label [[DOTBB7]]
+; CHECK: .bb7:
+; CHECK-NEXT: br i1 [[TMP3]], label [[DOTBB9:%.*]], label [[DOTBB10:%.*]]
+; CHECK: .bb8:
+; CHECK-NEXT: ret void
+; CHECK: .bb9:
+; CHECK-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX20]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX24]], align 4
+; CHECK-NEXT: [[ADD33_112:%.*]] = fadd float [[TMP9]], [[TMP8]]
+; CHECK-NEXT: [[ADD33_1_1:%.*]] = fadd float [[ADD33_112]], [[TMP6]]
+; CHECK-NEXT: [[ADD33_2_1:%.*]] = fadd float [[ADD33_1_1]], [[TMP7]]
+; CHECK-NEXT: br label [[DOTBB10]]
+; CHECK: .bb10:
+; CHECK-NEXT: [[TMP10]] = phi float [ [[ADD33_1_1]], [[DOTBB9]] ], [ [[TMP6]], [[DOTBB7]] ]
+; CHECK-NEXT: [[TMP11]] = phi float [ [[ADD33_2_1]], [[DOTBB9]] ], [ [[TMP7]], [[DOTBB7]] ]
+; CHECK-NEXT: br i1 [[CMP40]], label [[DOTBB11:%.*]], label [[DOTBB12]]
+; CHECK: .bb11:
+; CHECK-NEXT: store float [[TMP11]], float* [[ARRAYIDX3]], align 4
+; CHECK-NEXT: store float [[TMP10]], float* [[ARRAYIDX6]], align 4
+; CHECK-NEXT: br label [[DOTBB12]]
+; CHECK: .bb12:
+; CHECK-NEXT: [[SUB]] = add i32 [[I12_06]], -4
+; CHECK-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[SUB]], 0
+; CHECK-NEXT: br i1 [[CMP13]], label [[DOTBB3]], label [[DOTBB8]]
+;
%callA = alloca [258 x float], align 4
%callB = alloca [258 x float], align 4
%conv.i = uitofp i32 %iNumSteps to float
@@ -29,15 +98,6 @@ define void @MainKernel(i32 %iNumSteps, i32 %tid, i32 %base) {
%cmp135 = icmp sgt i32 %iNumSteps, 0
br i1 %cmp135, label %.bb3, label %.bb8
-; CHECK-LABEL: .bb3
-; CHECK: phi float
-; CHECK: phi float
-; CHECK: phi i32 {{.*}} [ %iNumSteps
-; CHECK-NOT: rA.sroa.[0-9].[0-9] = phi i32
-; CHECK-NOT: phi float
-; CHECK-NOT: phi i32
-; CHECK-LABEL: .bb4
-
.bb3:
%rA.sroa.8.0 = phi i32 [ %rA.sroa.8.2, %.bb12 ], [ %1, %.bb2 ]
%rA.sroa.0.0 = phi i32 [ %rA.sroa.0.2, %.bb12 ], [ %1, %.bb2 ]
@@ -66,14 +126,6 @@ define void @MainKernel(i32 %iNumSteps, i32 %tid, i32 %base) {
%14 = bitcast float %add33.2 to i32
br label %.bb5
-; CHECK-LABEL: .bb5
-; CHECK: phi float
-; CHECK: phi float
-; CHECK-NOT: rA.sroa.[0-9].[0-9] = phi i32
-; CHECK-NOT: phi float
-; CHECK-NOT: phi i32
-; CHECK-LABEL: .bb6
-
.bb5:
%rA.sroa.8.1 = phi i32 [ %12, %.bb4 ], [ %rA.sroa.8.0, %.bb3 ]
%rA.sroa.0.1 = phi i32 [ %14, %.bb4 ], [ %rA.sroa.0.0, %.bb3 ]
@@ -104,25 +156,11 @@ define void @MainKernel(i32 %iNumSteps, i32 %tid, i32 %base) {
%22 = bitcast float %add33.2.1 to i32
br label %.bb10
-; CHECK-LABEL: .bb10
-; CHECK: phi float
-; CHECK: phi float
-; CHECK-NOT: rA.sroa.[0-9].[0-9] = phi i32
-; CHECK-NOT: phi float
-; CHECK-NOT: phi i32
-; CHECK-LABEL: .bb11
-
.bb10:
%rA.sroa.8.2 = phi i32 [ %20, %.bb9 ], [ %rA.sroa.8.1, %.bb7 ]
%rA.sroa.0.2 = phi i32 [ %22, %.bb9 ], [ %rA.sroa.0.1, %.bb7 ]
br i1 %cmp40, label %.bb11, label %.bb12
-; CHECK-LABEL: .bb11
-; CHECK: store float
-; CHECK: store float
-; CHECK-NOT: store i32 %rA.sroa.[0-9].[0-9]
-; CHECK-LABEL: .bb12
-
.bb11:
store i32 %rA.sroa.0.2, i32* %2, align 4
store i32 %rA.sroa.8.2, i32* %3, align 4
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