[PATCH] D73870: [NFC] unsigned->Register in storeRegTo/loadRegFromStack

[Simon Moll via Phabricator via llvm-commits]

simoll created this revision.
simoll added reviewers: arsenm, craig.topper, uweigand, jpienaar, atanasyan, venkatra, robertlytton, dylanmckay, t.p.northover, kparzysz, tstellar, k-ishizaka.
Herald added subscribers: llvm-commits, kerbowa, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, jsji, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, fedor.sergeev, kbarton, hiraditya, nhaehnle, wdng, jvesely, nemanjai, sdardis, jyknight.
Herald added a project: LLVM.

This patch makes progress on the 'unsigned -> Register' rewrite for
`TargetInstrInfo::loadRegFromStack` and `TII::storeRegToStack`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73870

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/ARC/ARCInstrInfo.cpp
  llvm/lib/Target/ARC/ARCInstrInfo.h
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
  llvm/lib/Target/ARM/Thumb1InstrInfo.h
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/lib/Target/ARM/Thumb2InstrInfo.h
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.h
  llvm/lib/Target/BPF/BPFInstrInfo.cpp
  llvm/lib/Target/BPF/BPFInstrInfo.h
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.h
  llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
  llvm/lib/Target/Lanai/LanaiInstrInfo.h
  llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
  llvm/lib/Target/MSP430/MSP430InstrInfo.h
  llvm/lib/Target/Mips/Mips16InstrInfo.cpp
  llvm/lib/Target/Mips/Mips16InstrInfo.h
  llvm/lib/Target/Mips/MipsInstrInfo.h
  llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
  llvm/lib/Target/Mips/MipsSEInstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/Sparc/SparcInstrInfo.cpp
  llvm/lib/Target/Sparc/SparcInstrInfo.h
  llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.h
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/lib/Target/XCore/XCoreInstrInfo.cpp
  llvm/lib/Target/XCore/XCoreInstrInfo.h

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