[llvm] 2462626 - [X86] Cleanup the lrint/llrint/lround/llround tests a bit.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 2 11:47:28 PST 2020
Author: Craig Topper
Date: 2020-02-02T11:01:05-08:00
New Revision: 246262671f3d236f9349c13ad633c3c5844047f2
URL: https://github.com/llvm/llvm-project/commit/246262671f3d236f9349c13ad633c3c5844047f2
DIFF: https://github.com/llvm/llvm-project/commit/246262671f3d236f9349c13ad633c3c5844047f2.diff
LOG: [X86] Cleanup the lrint/llrint/lround/llround tests a bit.
We don't need tests for truncating the result. There's nothing
special about those truncates.
We can test llrint/llround for 64-bit and 32-bit targets in the same file.
Same with lrint/lround with i32 result result. lrint/lround with
64-bit result should only occur on a 64-bit target.
Add some missing tests for f80 conversions.
Added:
llvm/test/CodeGen/X86/lrint-conv-i64.ll
llvm/test/CodeGen/X86/lround-conv-i64.ll
Modified:
llvm/test/CodeGen/X86/llrint-conv.ll
llvm/test/CodeGen/X86/llround-conv.ll
llvm/test/CodeGen/X86/lrint-conv-i32.ll
llvm/test/CodeGen/X86/lround-conv-i32.ll
Removed:
llvm/test/CodeGen/X86/llrint-conv-i32.ll
llvm/test/CodeGen/X86/llround-conv-i32.ll
llvm/test/CodeGen/X86/lrint-conv.ll
llvm/test/CodeGen/X86/lround-conv.ll
################################################################################
diff --git a/llvm/test/CodeGen/X86/llrint-conv-i32.ll b/llvm/test/CodeGen/X86/llrint-conv-i32.ll
deleted file mode 100644
index de05af14fa16..000000000000
--- a/llvm/test/CodeGen/X86/llrint-conv-i32.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
-; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
-
-define i64 @testmsxs_builtin(float %x) {
-; CHECK-LABEL: testmsxs_builtin:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: flds {{[0-9]+}}(%esp)
-; CHECK-NEXT: fstps (%esp)
-; CHECK-NEXT: calll llrintf
-; CHECK-NEXT: popl %ecx
-; CHECK-NEXT: .cfi_def_cfa_offset 4
-; CHECK-NEXT: retl
-;
-; SSE2-LABEL: testmsxs_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: pushl %eax
-; SSE2-NEXT: .cfi_def_cfa_offset 8
-; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2-NEXT: movss %xmm0, (%esp)
-; SSE2-NEXT: calll llrintf
-; SSE2-NEXT: popl %ecx
-; SSE2-NEXT: .cfi_def_cfa_offset 4
-; SSE2-NEXT: retl
-entry:
- %0 = tail call i64 @llvm.llrint.f32(float %x)
- ret i64 %0
-}
-
-define i64 @testmsxd_builtin(double %x) {
-; CHECK-LABEL: testmsxd_builtin:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subl $8, %esp
-; CHECK-NEXT: .cfi_def_cfa_offset 12
-; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
-; CHECK-NEXT: fstpl (%esp)
-; CHECK-NEXT: calll llrint
-; CHECK-NEXT: addl $8, %esp
-; CHECK-NEXT: .cfi_def_cfa_offset 4
-; CHECK-NEXT: retl
-;
-; SSE2-LABEL: testmsxd_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: subl $8, %esp
-; SSE2-NEXT: .cfi_def_cfa_offset 12
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: movsd %xmm0, (%esp)
-; SSE2-NEXT: calll llrint
-; SSE2-NEXT: addl $8, %esp
-; SSE2-NEXT: .cfi_def_cfa_offset 4
-; SSE2-NEXT: retl
-entry:
- %0 = tail call i64 @llvm.llrint.f64(double %x)
- ret i64 %0
-}
-
-declare i64 @llvm.llrint.f32(float) nounwind readnone
-declare i64 @llvm.llrint.f64(double) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/llrint-conv.ll b/llvm/test/CodeGen/X86/llrint-conv.ll
index bcdea81b023a..1472af1639b2 100644
--- a/llvm/test/CodeGen/X86/llrint-conv.ll
+++ b/llvm/test/CodeGen/X86/llrint-conv.ll
@@ -1,78 +1,96 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
-
-define i32 @testmsws(float %x) {
-; CHECK-LABEL: testmsws:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq llrintf
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.llrint.f32(float %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
define i64 @testmsxs(float %x) {
-; CHECK-LABEL: testmsxs:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp llrintf # TAILCALL
+; X86-LABEL: testmsxs:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %eax
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: flds {{[0-9]+}}(%esp)
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll llrintf
+; X86-NEXT: popl %ecx
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; SSE2-LABEL: testmsxs:
+; SSE2: # %bb.0: # %entry
+; SSE2-NEXT: pushl %eax
+; SSE2-NEXT: .cfi_def_cfa_offset 8
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: movss %xmm0, (%esp)
+; SSE2-NEXT: calll llrintf
+; SSE2-NEXT: popl %ecx
+; SSE2-NEXT: .cfi_def_cfa_offset 4
+; SSE2-NEXT: retl
+;
+; X64-LABEL: testmsxs:
+; X64: # %bb.0: # %entry
+; X64-NEXT: jmp llrintf # TAILCALL
entry:
%0 = tail call i64 @llvm.llrint.f32(float %x)
ret i64 %0
}
-define i32 @testmswd(double %x) {
-; CHECK-LABEL: testmswd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq llrint
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.llrint.f64(double %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
define i64 @testmsxd(double %x) {
-; CHECK-LABEL: testmsxd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp llrint # TAILCALL
+; X86-LABEL: testmsxd:
+; X86: # %bb.0: # %entry
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: .cfi_def_cfa_offset 12
+; X86-NEXT: fldl {{[0-9]+}}(%esp)
+; X86-NEXT: fstpl (%esp)
+; X86-NEXT: calll llrint
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; SSE2-LABEL: testmsxd:
+; SSE2: # %bb.0: # %entry
+; SSE2-NEXT: subl $8, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 12
+; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-NEXT: movsd %xmm0, (%esp)
+; SSE2-NEXT: calll llrint
+; SSE2-NEXT: addl $8, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 4
+; SSE2-NEXT: retl
+;
+; X64-LABEL: testmsxd:
+; X64: # %bb.0: # %entry
+; X64-NEXT: jmp llrint # TAILCALL
entry:
%0 = tail call i64 @llvm.llrint.f64(double %x)
ret i64 %0
}
-define dso_local i32 @testmswl(x86_fp80 %x) {
-; CHECK-LABEL: testmswl:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq llrintl
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.llrint.f80(x86_fp80 %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define dso_local i64 @testmsll(x86_fp80 %x) {
-; CHECK-LABEL: testmsll:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp llrintl # TAILCALL
+define i64 @testmsll(x86_fp80 %x) {
+; X86-LABEL: testmsll:
+; X86: # %bb.0: # %entry
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: .cfi_def_cfa_offset 16
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fstpt (%esp)
+; X86-NEXT: calll llrintl
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; SSE2-LABEL: testmsll:
+; SSE2: # %bb.0: # %entry
+; SSE2-NEXT: subl $12, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 16
+; SSE2-NEXT: fldt {{[0-9]+}}(%esp)
+; SSE2-NEXT: fstpt (%esp)
+; SSE2-NEXT: calll llrintl
+; SSE2-NEXT: addl $12, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 4
+; SSE2-NEXT: retl
+;
+; X64-LABEL: testmsll:
+; X64: # %bb.0: # %entry
+; X64-NEXT: jmp llrintl # TAILCALL
entry:
%0 = tail call i64 @llvm.llrint.f80(x86_fp80 %x)
ret i64 %0
diff --git a/llvm/test/CodeGen/X86/llround-conv-i32.ll b/llvm/test/CodeGen/X86/llround-conv-i32.ll
deleted file mode 100644
index f3297c5ebf79..000000000000
--- a/llvm/test/CodeGen/X86/llround-conv-i32.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
-; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
-
-define i64 @testmsxs_builtin(float %x) {
-; CHECK-LABEL: testmsxs_builtin:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushl %eax
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: flds {{[0-9]+}}(%esp)
-; CHECK-NEXT: fstps (%esp)
-; CHECK-NEXT: calll llroundf
-; CHECK-NEXT: popl %ecx
-; CHECK-NEXT: .cfi_def_cfa_offset 4
-; CHECK-NEXT: retl
-;
-; SSE2-LABEL: testmsxs_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: pushl %eax
-; SSE2-NEXT: .cfi_def_cfa_offset 8
-; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2-NEXT: movss %xmm0, (%esp)
-; SSE2-NEXT: calll llroundf
-; SSE2-NEXT: popl %ecx
-; SSE2-NEXT: .cfi_def_cfa_offset 4
-; SSE2-NEXT: retl
-entry:
- %0 = tail call i64 @llvm.llround.f32(float %x)
- ret i64 %0
-}
-
-define i64 @testmsxd_builtin(double %x) {
-; CHECK-LABEL: testmsxd_builtin:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subl $8, %esp
-; CHECK-NEXT: .cfi_def_cfa_offset 12
-; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
-; CHECK-NEXT: fstpl (%esp)
-; CHECK-NEXT: calll llround
-; CHECK-NEXT: addl $8, %esp
-; CHECK-NEXT: .cfi_def_cfa_offset 4
-; CHECK-NEXT: retl
-;
-; SSE2-LABEL: testmsxd_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: subl $8, %esp
-; SSE2-NEXT: .cfi_def_cfa_offset 12
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: movsd %xmm0, (%esp)
-; SSE2-NEXT: calll llround
-; SSE2-NEXT: addl $8, %esp
-; SSE2-NEXT: .cfi_def_cfa_offset 4
-; SSE2-NEXT: retl
-entry:
- %0 = tail call i64 @llvm.llround.f64(double %x)
- ret i64 %0
-}
-
-declare i64 @llvm.llround.f32(float) nounwind readnone
-declare i64 @llvm.llround.f64(double) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/llround-conv.ll b/llvm/test/CodeGen/X86/llround-conv.ll
index 459ae4abb2cd..d80f227eebff 100644
--- a/llvm/test/CodeGen/X86/llround-conv.ll
+++ b/llvm/test/CodeGen/X86/llround-conv.ll
@@ -1,78 +1,96 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
-
-define i32 @testmsws(float %x) {
-; CHECK-LABEL: testmsws:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq llroundf
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.llround.f32(float %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
define i64 @testmsxs(float %x) {
-; CHECK-LABEL: testmsxs:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp llroundf # TAILCALL
+; X86-LABEL: testmsxs:
+; X86: # %bb.0: # %entry
+; X86-NEXT: pushl %eax
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: flds {{[0-9]+}}(%esp)
+; X86-NEXT: fstps (%esp)
+; X86-NEXT: calll llroundf
+; X86-NEXT: popl %ecx
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; SSE2-LABEL: testmsxs:
+; SSE2: # %bb.0: # %entry
+; SSE2-NEXT: pushl %eax
+; SSE2-NEXT: .cfi_def_cfa_offset 8
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: movss %xmm0, (%esp)
+; SSE2-NEXT: calll llroundf
+; SSE2-NEXT: popl %ecx
+; SSE2-NEXT: .cfi_def_cfa_offset 4
+; SSE2-NEXT: retl
+;
+; X64-LABEL: testmsxs:
+; X64: # %bb.0: # %entry
+; X64-NEXT: jmp llroundf # TAILCALL
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}
-define i32 @testmswd(double %x) {
-; CHECK-LABEL: testmswd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq llround
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.llround.f64(double %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
define i64 @testmsxd(double %x) {
-; CHECK-LABEL: testmsxd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp llround # TAILCALL
+; X86-LABEL: testmsxd:
+; X86: # %bb.0: # %entry
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: .cfi_def_cfa_offset 12
+; X86-NEXT: fldl {{[0-9]+}}(%esp)
+; X86-NEXT: fstpl (%esp)
+; X86-NEXT: calll llround
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; SSE2-LABEL: testmsxd:
+; SSE2: # %bb.0: # %entry
+; SSE2-NEXT: subl $8, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 12
+; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-NEXT: movsd %xmm0, (%esp)
+; SSE2-NEXT: calll llround
+; SSE2-NEXT: addl $8, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 4
+; SSE2-NEXT: retl
+;
+; X64-LABEL: testmsxd:
+; X64: # %bb.0: # %entry
+; X64-NEXT: jmp llround # TAILCALL
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}
-define i32 @testmswl(x86_fp80 %x) {
-; CHECK-LABEL: testmswl:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq llroundl
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.llround.f80(x86_fp80 %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
define i64 @testmsll(x86_fp80 %x) {
-; CHECK-LABEL: testmsll:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp llroundl # TAILCALL
+; X86-LABEL: testmsll:
+; X86: # %bb.0: # %entry
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: .cfi_def_cfa_offset 16
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fstpt (%esp)
+; X86-NEXT: calll llroundl
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: retl
+;
+; SSE2-LABEL: testmsll:
+; SSE2: # %bb.0: # %entry
+; SSE2-NEXT: subl $12, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 16
+; SSE2-NEXT: fldt {{[0-9]+}}(%esp)
+; SSE2-NEXT: fstpt (%esp)
+; SSE2-NEXT: calll llroundl
+; SSE2-NEXT: addl $12, %esp
+; SSE2-NEXT: .cfi_def_cfa_offset 4
+; SSE2-NEXT: retl
+;
+; X64-LABEL: testmsll:
+; X64: # %bb.0: # %entry
+; X64-NEXT: jmp llroundl # TAILCALL
entry:
%0 = tail call i64 @llvm.llround.f80(x86_fp80 %x)
ret i64 %0
diff --git a/llvm/test/CodeGen/X86/lrint-conv-i32.ll b/llvm/test/CodeGen/X86/lrint-conv-i32.ll
index 7bc8c36741f5..888160112e53 100644
--- a/llvm/test/CodeGen/X86/lrint-conv-i32.ll
+++ b/llvm/test/CodeGen/X86/lrint-conv-i32.ll
@@ -1,32 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
-; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,X64
-define i32 @testmsws_builtin(float %x) {
-; CHECK-LABEL: testmsws_builtin:
+define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lrintf # TAILCALL
-;
-; SSE2-LABEL: testmsws_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: jmp lrintf # TAILCALL
entry:
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
ret i32 %0
}
-define i32 @testmswd_builtin(double %x) {
-; CHECK-LABEL: testmswd_builtin:
+define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lrint # TAILCALL
-;
-; SSE2-LABEL: testmswd_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: jmp lrint # TAILCALL
entry:
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
ret i32 %0
}
+define i32 @testmsll(x86_fp80 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lrintl # TAILCALL
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f80(x86_fp80 %x)
+ ret i32 %0
+}
+
declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
+declare i32 @llvm.lrint.i32.f80(x86_fp80) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/lrint-conv-i64.ll b/llvm/test/CodeGen/X86/lrint-conv-i64.ll
new file mode 100644
index 000000000000..1b12edd43c51
--- /dev/null
+++ b/llvm/test/CodeGen/X86/lrint-conv-i64.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lrintf # TAILCALL
+entry:
+ %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
+ ret i64 %0
+}
+
+define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lrint # TAILCALL
+entry:
+ %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
+ ret i64 %0
+}
+
+define i64 @testmsll(x86_fp80 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lrintl # TAILCALL
+entry:
+ %0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
+ ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
+declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
+declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/lrint-conv.ll b/llvm/test/CodeGen/X86/lrint-conv.ll
deleted file mode 100644
index a34c31e889d5..000000000000
--- a/llvm/test/CodeGen/X86/lrint-conv.ll
+++ /dev/null
@@ -1,83 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
-
-define i32 @testmsws(float %x) {
-; CHECK-LABEL: testmsws:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq lrintf
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define i64 @testmsxs(float %x) {
-; CHECK-LABEL: testmsxs:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp lrintf # TAILCALL
-entry:
- %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
- ret i64 %0
-}
-
-define i32 @testmswd(double %x) {
-; CHECK-LABEL: testmswd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq lrint
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define i64 @testmsxd(double %x) {
-; CHECK-LABEL: testmsxd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp lrint # TAILCALL
-entry:
- %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
- ret i64 %0
-}
-
-define dso_local i32 @testmswl(x86_fp80 %x) {
-; CHECK-LABEL: testmswl:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq lrintl
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define dso_local i64 @testmsll(x86_fp80 %x) {
-; CHECK-LABEL: testmsll:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp lrintl # TAILCALL
-entry:
- %0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
- ret i64 %0
-}
-
-declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
-declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
-declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/lround-conv-i32.ll b/llvm/test/CodeGen/X86/lround-conv-i32.ll
index 66fea71b3be6..c9b5ff0b1ee0 100644
--- a/llvm/test/CodeGen/X86/lround-conv-i32.ll
+++ b/llvm/test/CodeGen/X86/lround-conv-i32.ll
@@ -1,32 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
-; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,X64
-define i32 @testmsws_builtin(float %x) {
-; CHECK-LABEL: testmsws_builtin:
+define i32 @testmsws(float %x) {
+; CHECK-LABEL: testmsws:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lroundf # TAILCALL
-;
-; SSE2-LABEL: testmsws_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: jmp lroundf # TAILCALL
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
ret i32 %0
}
-define i32 @testmswd_builtin(double %x) {
-; CHECK-LABEL: testmswd_builtin:
+define i32 @testmswd(double %x) {
+; CHECK-LABEL: testmswd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: jmp lround # TAILCALL
-;
-; SSE2-LABEL: testmswd_builtin:
-; SSE2: # %bb.0: # %entry
-; SSE2-NEXT: jmp lround # TAILCALL
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
ret i32 %0
}
+define i32 @testmsll(x86_fp80 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lroundl # TAILCALL
+entry:
+ %0 = tail call i32 @llvm.lround.i32.f80(x86_fp80 %x)
+ ret i32 %0
+}
+
declare i32 @llvm.lround.i32.f32(float) nounwind readnone
declare i32 @llvm.lround.i32.f64(double) nounwind readnone
+declare i32 @llvm.lround.i32.f80(x86_fp80) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/lround-conv-i64.ll b/llvm/test/CodeGen/X86/lround-conv-i64.ll
new file mode 100644
index 000000000000..cd4c4994f7b9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/lround-conv-i64.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define i64 @testmsxs(float %x) {
+; CHECK-LABEL: testmsxs:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lroundf # TAILCALL
+entry:
+ %0 = tail call i64 @llvm.lround.i64.f32(float %x)
+ ret i64 %0
+}
+
+define i64 @testmsxd(double %x) {
+; CHECK-LABEL: testmsxd:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lround # TAILCALL
+entry:
+ %0 = tail call i64 @llvm.lround.i64.f64(double %x)
+ ret i64 %0
+}
+
+define i64 @testmsll(x86_fp80 %x) {
+; CHECK-LABEL: testmsll:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: jmp lroundl # TAILCALL
+entry:
+ %0 = tail call i64 @llvm.lround.i64.f80(x86_fp80 %x)
+ ret i64 %0
+}
+
+declare i64 @llvm.lround.i64.f32(float) nounwind readnone
+declare i64 @llvm.lround.i64.f64(double) nounwind readnone
+declare i64 @llvm.lround.i64.f80(x86_fp80) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/lround-conv.ll b/llvm/test/CodeGen/X86/lround-conv.ll
deleted file mode 100644
index 34f9ebef7cc5..000000000000
--- a/llvm/test/CodeGen/X86/lround-conv.ll
+++ /dev/null
@@ -1,83 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
-
-define i32 @testmsws(float %x) {
-; CHECK-LABEL: testmsws:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq lroundf
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.lround.i64.f32(float %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define i64 @testmsxs(float %x) {
-; CHECK-LABEL: testmsxs:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp lroundf # TAILCALL
-entry:
- %0 = tail call i64 @llvm.lround.i64.f32(float %x)
- ret i64 %0
-}
-
-define i32 @testmswd(double %x) {
-; CHECK-LABEL: testmswd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: callq lround
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.lround.i64.f64(double %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define i64 @testmsxd(double %x) {
-; CHECK-LABEL: testmsxd:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp lround # TAILCALL
-entry:
- %0 = tail call i64 @llvm.lround.i64.f64(double %x)
- ret i64 %0
-}
-
-define i32 @testmswl(x86_fp80 %x) {
-; CHECK-LABEL: testmswl:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
-; CHECK-NEXT: fstpt (%rsp)
-; CHECK-NEXT: callq lroundl
-; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
-entry:
- %0 = tail call i64 @llvm.lround.i64.f80(x86_fp80 %x)
- %conv = trunc i64 %0 to i32
- ret i32 %conv
-}
-
-define i64 @testmsll(x86_fp80 %x) {
-; CHECK-LABEL: testmsll:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: jmp lroundl # TAILCALL
-entry:
- %0 = tail call i64 @llvm.lround.i64.f80(x86_fp80 %x)
- ret i64 %0
-}
-
-declare i64 @llvm.lround.i64.f32(float) nounwind readnone
-declare i64 @llvm.lround.i64.f64(double) nounwind readnone
-declare i64 @llvm.lround.i64.f80(x86_fp80) nounwind readnone
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