[llvm] 17e91b7 - [X86][SSE] combineBitcastvxi1 - add pre-AVX512 v64i1 handling
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 2 10:00:53 PST 2020
Author: Simon Pilgrim
Date: 2020-02-02T18:00:09Z
New Revision: 17e91b7dd246690fd68efe00e24f8c46f755915e
URL: https://github.com/llvm/llvm-project/commit/17e91b7dd246690fd68efe00e24f8c46f755915e
DIFF: https://github.com/llvm/llvm-project/commit/17e91b7dd246690fd68efe00e24f8c46f755915e.diff
LOG: [X86][SSE] combineBitcastvxi1 - add pre-AVX512 v64i1 handling
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
llvm/test/CodeGen/X86/bitcast-vector-bool.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f8428beb4bab..cd98b82d120b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36441,7 +36441,14 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
case MVT::v64i1:
// If we have AVX512F, but not AVX512BW and the input is truncated from
// v64i8 checked earlier. Then split the input and make two pmovmskbs.
- if (Subtarget.hasAVX512() && !Subtarget.hasBWI()) {
+ if (Subtarget.hasAVX512()) {
+ if (Subtarget.hasBWI())
+ return SDValue();
+ SExtVT = MVT::v64i8;
+ break;
+ }
+ // Split if this is a <64 x i8> comparison result.
+ if (checkBitcastSrcVectorSize(Src, 512)) {
SExtVT = MVT::v64i8;
break;
}
diff --git a/llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll b/llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
index 29499848eb48..d24a735ce751 100644
--- a/llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
+++ b/llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
@@ -534,28 +534,28 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x floa
define i64 @v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i8> %d) {
; SSE-LABEL: v64i8:
; SSE: # %bb.0:
-; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
-; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
-; SSE-NEXT: pcmpgtb %xmm7, %xmm3
-; SSE-NEXT: pcmpgtb %xmm6, %xmm2
-; SSE-NEXT: pcmpgtb %xmm5, %xmm1
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
+; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: pcmpgtb %xmm4, %xmm0
-; SSE-NEXT: pcmpgtb {{[0-9]+}}(%rsp), %xmm9
-; SSE-NEXT: pand %xmm3, %xmm9
-; SSE-NEXT: pcmpgtb {{[0-9]+}}(%rsp), %xmm8
-; SSE-NEXT: pand %xmm2, %xmm8
+; SSE-NEXT: pcmpgtb %xmm5, %xmm1
+; SSE-NEXT: pcmpgtb %xmm6, %xmm2
+; SSE-NEXT: pcmpgtb %xmm7, %xmm3
; SSE-NEXT: pcmpgtb {{[0-9]+}}(%rsp), %xmm11
-; SSE-NEXT: pand %xmm1, %xmm11
+; SSE-NEXT: pand %xmm0, %xmm11
; SSE-NEXT: pcmpgtb {{[0-9]+}}(%rsp), %xmm10
-; SSE-NEXT: pand %xmm0, %xmm10
-; SSE-NEXT: pmovmskb %xmm10, %eax
-; SSE-NEXT: pmovmskb %xmm11, %ecx
+; SSE-NEXT: pand %xmm1, %xmm10
+; SSE-NEXT: pcmpgtb {{[0-9]+}}(%rsp), %xmm9
+; SSE-NEXT: pand %xmm2, %xmm9
+; SSE-NEXT: pcmpgtb {{[0-9]+}}(%rsp), %xmm8
+; SSE-NEXT: pand %xmm3, %xmm8
+; SSE-NEXT: pmovmskb %xmm11, %eax
+; SSE-NEXT: pmovmskb %xmm10, %ecx
; SSE-NEXT: shll $16, %ecx
; SSE-NEXT: orl %eax, %ecx
-; SSE-NEXT: pmovmskb %xmm8, %edx
-; SSE-NEXT: pmovmskb %xmm9, %eax
+; SSE-NEXT: pmovmskb %xmm9, %edx
+; SSE-NEXT: pmovmskb %xmm8, %eax
; SSE-NEXT: shll $16, %eax
; SSE-NEXT: orl %edx, %eax
; SSE-NEXT: shlq $32, %rax
@@ -599,12 +599,12 @@ define i64 @v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i8> %d) {
;
; AVX2-LABEL: v64i8:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpgtb %ymm7, %ymm5, %ymm2
-; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
+; AVX2-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtb %ymm6, %ymm4, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpcmpgtb %ymm7, %ymm5, %ymm2
+; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vpmovmskb %ymm0, %ecx
; AVX2-NEXT: vpmovmskb %ymm1, %eax
; AVX2-NEXT: shlq $32, %rax
diff --git a/llvm/test/CodeGen/X86/bitcast-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-vector-bool.ll
index e7a457e11a80..aa096f80bbfe 100644
--- a/llvm/test/CodeGen/X86/bitcast-vector-bool.ll
+++ b/llvm/test/CodeGen/X86/bitcast-vector-bool.ll
@@ -583,256 +583,17 @@ define i16 @bitcast_v32i16_to_v2i16(<32 x i16> %a0) nounwind {
define i32 @bitcast_v64i8_to_v2i32(<64 x i8> %a0) nounwind {
; SSE2-SSSE3-LABEL: bitcast_v64i8_to_v2i32:
; SSE2-SSSE3: # %bb.0:
-; SSE2-SSSE3-NEXT: pxor %xmm4, %xmm4
-; SSE2-SSSE3-NEXT: pxor %xmm5, %xmm5
-; SSE2-SSSE3-NEXT: pcmpgtb %xmm3, %xmm5
-; SSE2-SSSE3-NEXT: movdqa %xmm5, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: pxor %xmm3, %xmm3
-; SSE2-SSSE3-NEXT: pcmpgtb %xmm2, %xmm3
-; SSE2-SSSE3-NEXT: movdqa %xmm3, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm2
-; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm2
-; SSE2-SSSE3-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: pcmpgtb %xmm0, %xmm4
-; SSE2-SSSE3-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $4, %ecx
-; SSE2-SSSE3-NEXT: orl %eax, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: shll $5, %eax
-; SSE2-SSSE3-NEXT: orl %ecx, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $6, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $7, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $8, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $9, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $10, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $11, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $12, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $13, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $14, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: shll $15, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: orl %eax, %edx
-; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $4, %ecx
-; SSE2-SSSE3-NEXT: orl %eax, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: shll $5, %eax
-; SSE2-SSSE3-NEXT: orl %ecx, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $6, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $7, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $8, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $9, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $10, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $11, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $12, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $13, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $14, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: shll $15, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: orl %eax, %edx
-; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $4, %ecx
-; SSE2-SSSE3-NEXT: orl %eax, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: shll $5, %eax
-; SSE2-SSSE3-NEXT: orl %ecx, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $6, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $7, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $8, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $9, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $10, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $11, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $12, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $13, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $14, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: shll $15, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: orl %eax, %edx
-; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rcx,%rax,2), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,4), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: leal (%rax,%rcx,8), %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $4, %ecx
+; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax
+; SSE2-SSSE3-NEXT: pmovmskb %xmm1, %ecx
+; SSE2-SSSE3-NEXT: shll $16, %ecx
; SSE2-SSSE3-NEXT: orl %eax, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-SSSE3-NEXT: andl $1, %eax
-; SSE2-SSSE3-NEXT: shll $5, %eax
-; SSE2-SSSE3-NEXT: orl %ecx, %eax
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $6, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $7, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $8, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $9, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $10, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $11, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $12, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: andl $1, %edx
-; SSE2-SSSE3-NEXT: shll $13, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
-; SSE2-SSSE3-NEXT: andl $1, %ecx
-; SSE2-SSSE3-NEXT: shll $14, %ecx
-; SSE2-SSSE3-NEXT: orl %edx, %ecx
-; SSE2-SSSE3-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
-; SSE2-SSSE3-NEXT: shll $15, %edx
-; SSE2-SSSE3-NEXT: orl %ecx, %edx
+; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax
+; SSE2-SSSE3-NEXT: pmovmskb %xmm3, %edx
+; SSE2-SSSE3-NEXT: shll $16, %edx
; SSE2-SSSE3-NEXT: orl %eax, %edx
-; SSE2-SSSE3-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
-; SSE2-SSSE3-NEXT: movdqa -{{[0-9]+}}(%rsp), %xmm0
-; SSE2-SSSE3-NEXT: movd %xmm0, %ecx
+; SSE2-SSSE3-NEXT: shlq $32, %rdx
+; SSE2-SSSE3-NEXT: orq %rcx, %rdx
+; SSE2-SSSE3-NEXT: movq %rdx, %xmm0
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE2-SSSE3-NEXT: movd %xmm0, %eax
; SSE2-SSSE3-NEXT: addl %ecx, %eax
@@ -840,522 +601,24 @@ define i32 @bitcast_v64i8_to_v2i32(<64 x i8> %a0) nounwind {
;
; AVX1-LABEL: bitcast_v64i8_to_v2i32:
; AVX1: # %bb.0:
-; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm3
-; AVX1-NEXT: vpextrb $1, %xmm3, %eax
-; AVX1-NEXT: andl $1, %eax
-; AVX1-NEXT: vpextrb $0, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: leal (%rcx,%rax,2), %eax
-; AVX1-NEXT: vpextrb $2, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: leal (%rax,%rcx,4), %eax
-; AVX1-NEXT: vpextrb $3, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: leal (%rax,%rcx,8), %eax
-; AVX1-NEXT: vpextrb $4, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $4, %ecx
-; AVX1-NEXT: orl %eax, %ecx
-; AVX1-NEXT: vpextrb $5, %xmm3, %eax
-; AVX1-NEXT: andl $1, %eax
-; AVX1-NEXT: shll $5, %eax
-; AVX1-NEXT: orl %ecx, %eax
-; AVX1-NEXT: vpextrb $6, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $6, %ecx
-; AVX1-NEXT: vpextrb $7, %xmm3, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $7, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $8, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $8, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $9, %xmm3, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $9, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $10, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $10, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $11, %xmm3, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $11, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $12, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $12, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $13, %xmm3, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $13, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $14, %xmm3, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $14, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $15, %xmm3, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $15, %edx
-; AVX1-NEXT: orl %ecx, %edx
+; AVX1-NEXT: vpmovmskb %xmm1, %eax
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
-; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vpextrb $0, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
+; AVX1-NEXT: vpmovmskb %xmm1, %ecx
; AVX1-NEXT: shll $16, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $1, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $17, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $2, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $18, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $3, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $19, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $4, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $20, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $5, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $21, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $6, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $22, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $7, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $23, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $8, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $24, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $9, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $25, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $10, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $26, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $11, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $27, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $12, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $28, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $13, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $29, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $14, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $30, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $15, %xmm1, %edx
-; AVX1-NEXT: shll $31, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: orl %eax, %edx
-; AVX1-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm1
-; AVX1-NEXT: vpextrb $1, %xmm1, %eax
-; AVX1-NEXT: andl $1, %eax
-; AVX1-NEXT: vpextrb $0, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: leal (%rcx,%rax,2), %eax
-; AVX1-NEXT: vpextrb $2, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: leal (%rax,%rcx,4), %eax
-; AVX1-NEXT: vpextrb $3, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: leal (%rax,%rcx,8), %eax
-; AVX1-NEXT: vpextrb $4, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $4, %ecx
; AVX1-NEXT: orl %eax, %ecx
-; AVX1-NEXT: vpextrb $5, %xmm1, %eax
-; AVX1-NEXT: andl $1, %eax
-; AVX1-NEXT: shll $5, %eax
-; AVX1-NEXT: orl %ecx, %eax
-; AVX1-NEXT: vpextrb $6, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $6, %ecx
-; AVX1-NEXT: vpextrb $7, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $7, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $8, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $8, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $9, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $9, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $10, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $10, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $11, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $11, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $12, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $12, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $13, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $13, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $14, %xmm1, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $14, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $15, %xmm1, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $15, %edx
-; AVX1-NEXT: orl %ecx, %edx
+; AVX1-NEXT: vpmovmskb %xmm0, %edx
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
-; AVX1-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vpextrb $0, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $16, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $1, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $17, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $2, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $18, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $3, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $19, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $4, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $20, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $5, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $21, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $6, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $22, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $7, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $23, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $8, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $24, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $9, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $25, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $10, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $26, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $11, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $27, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $12, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $28, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $13, %xmm0, %edx
-; AVX1-NEXT: andl $1, %edx
-; AVX1-NEXT: shll $29, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: vpextrb $14, %xmm0, %ecx
-; AVX1-NEXT: andl $1, %ecx
-; AVX1-NEXT: shll $30, %ecx
-; AVX1-NEXT: orl %edx, %ecx
-; AVX1-NEXT: vpextrb $15, %xmm0, %edx
-; AVX1-NEXT: shll $31, %edx
-; AVX1-NEXT: orl %ecx, %edx
-; AVX1-NEXT: orl %eax, %edx
-; AVX1-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; AVX1-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm0
-; AVX1-NEXT: vmovd %xmm0, %ecx
-; AVX1-NEXT: vpextrd $1, %xmm0, %eax
+; AVX1-NEXT: vpmovmskb %xmm0, %eax
+; AVX1-NEXT: shll $16, %eax
+; AVX1-NEXT: orl %edx, %eax
; AVX1-NEXT: addl %ecx, %eax
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: bitcast_v64i8_to_v2i32:
; AVX2: # %bb.0:
-; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX2-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: vpextrb $1, %xmm1, %eax
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: vpextrb $0, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rcx,%rax,2), %eax
-; AVX2-NEXT: vpextrb $2, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rax,%rcx,4), %eax
-; AVX2-NEXT: vpextrb $3, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rax,%rcx,8), %eax
-; AVX2-NEXT: vpextrb $4, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $4, %ecx
-; AVX2-NEXT: orl %eax, %ecx
-; AVX2-NEXT: vpextrb $5, %xmm1, %eax
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: shll $5, %eax
-; AVX2-NEXT: orl %ecx, %eax
-; AVX2-NEXT: vpextrb $6, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $6, %ecx
-; AVX2-NEXT: vpextrb $7, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $7, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $8, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $8, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $9, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $9, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $10, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $10, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $11, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $11, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $12, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $12, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $13, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $13, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $14, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $14, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $15, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $15, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
-; AVX2-NEXT: vpextrb $0, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $16, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $1, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $17, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $2, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $18, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $3, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $19, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $4, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $20, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $5, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $21, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $6, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $22, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $7, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $23, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $8, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $24, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $9, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $25, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $10, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $26, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $11, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $27, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $12, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $28, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $13, %xmm1, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $29, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $14, %xmm1, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $30, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $15, %xmm1, %edx
-; AVX2-NEXT: shll $31, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: orl %eax, %edx
-; AVX2-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
-; AVX2-NEXT: vpextrb $1, %xmm0, %eax
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: vpextrb $0, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rcx,%rax,2), %eax
-; AVX2-NEXT: vpextrb $2, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rax,%rcx,4), %eax
-; AVX2-NEXT: vpextrb $3, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: leal (%rax,%rcx,8), %eax
-; AVX2-NEXT: vpextrb $4, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $4, %ecx
-; AVX2-NEXT: orl %eax, %ecx
-; AVX2-NEXT: vpextrb $5, %xmm0, %eax
-; AVX2-NEXT: andl $1, %eax
-; AVX2-NEXT: shll $5, %eax
-; AVX2-NEXT: orl %ecx, %eax
-; AVX2-NEXT: vpextrb $6, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $6, %ecx
-; AVX2-NEXT: vpextrb $7, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $7, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $8, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $8, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $9, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $9, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $10, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $10, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $11, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $11, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $12, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $12, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $13, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $13, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $14, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $14, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $15, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $15, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
-; AVX2-NEXT: vpextrb $0, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $16, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $1, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $17, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $2, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $18, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $3, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $19, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $4, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $20, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $5, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $21, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $6, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $22, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $7, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $23, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $8, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $24, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $9, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $25, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $10, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $26, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $11, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $27, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $12, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $28, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $13, %xmm0, %edx
-; AVX2-NEXT: andl $1, %edx
-; AVX2-NEXT: shll $29, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: vpextrb $14, %xmm0, %ecx
-; AVX2-NEXT: andl $1, %ecx
-; AVX2-NEXT: shll $30, %ecx
-; AVX2-NEXT: orl %edx, %ecx
-; AVX2-NEXT: vpextrb $15, %xmm0, %edx
-; AVX2-NEXT: shll $31, %edx
-; AVX2-NEXT: orl %ecx, %edx
-; AVX2-NEXT: orl %eax, %edx
-; AVX2-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; AVX2-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm0
-; AVX2-NEXT: vmovd %xmm0, %ecx
-; AVX2-NEXT: vpextrd $1, %xmm0, %eax
+; AVX2-NEXT: vpmovmskb %ymm1, %ecx
+; AVX2-NEXT: vpmovmskb %ymm0, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
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