[PATCH] D73749: [LegalizeTypes][X86] Add a new strategy for type legalizing f16 type that softens it to i16, but promotes to f32 around arithmetic ops.

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked an inline comment as done.
craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:2766
+
+SDValue DAGTypeLegalizer::SoftPromoteHalfOp_INSERT_VECTOR_ELT(SDNode *N,
+                                                              unsigned OpNo) {
----------------
efriedma wrote:
> Is SoftPromoteHalfOp_INSERT_VECTOR_ELT actually reachable?  If the operand is a half-float, the result would have to be a half vector, and we would split that, I think?
You're right. I'm not sure why I put that in there. I'll remove.


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https://reviews.llvm.org/D73749