[PATCH] D72842: [GlobalISel] Tweak lowering of G_SMULO/G_UMULO

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


================
Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2012
     Register HiPart = MRI.createGenericVirtualRegister(Ty);
-    MIRBuilder.buildInstr(Opcode)
-      .addDef(HiPart)
-      .addUse(LHS)
-      .addUse(RHS);
+    MIRBuilder.buildInstr(Opcode, {HiPart}, {LHS, RHS});
 
----------------
We can go a bit further here and just do:
```
auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS});
```


================
Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2023
       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
-      MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
-        .addDef(Shifted)
-        .addUse(Res)
-        .addUse(ShiftAmt);
+      MIRBuilder.buildAShr(Shifted, Res, ShiftAmt);
       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
----------------
Same cleanup here:
```
auto ShiftAmt = MIRBuilder.buildConstant(Ty, ShiftAmt);
auto Shifted = MIRBuilder.buildAshr(Ty, Res, ShiftAmt);
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72842/new/

https://reviews.llvm.org/D72842