[PATCH] D71774: [RISCV] Optimize seteq/setne pattern expansions for better code size

[weiwei via Phabricator via llvm-commits]

wwei added a comment.



In D71774#1821760 <https://reviews.llvm.org/D71774#1821760>, @lenary wrote:

> This seems like a fun issue:
>
> - `addi` is compressible
> - `xor` is almost certainly easier to analyse (from the view of `KnownBits` and the like).
>
>   Have you seen any regressions in code generation from this change?


No, there's no any regressions. For the case where the register is compared with an immediate value (equal or unequal), using `xori` or `addi` with neg imm in the pattern `seteq` or `setne`  is equivalent, in order to get a result equal to 0 or not equal to 0.


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https://reviews.llvm.org/D71774