[PATCH] D73496: [IRCE] Use SCEVExpander to modify loop bound

Denis Antrushin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 30 08:04:37 PST 2020


dantrushin updated this revision to Diff 241461.
dantrushin added a comment.

Make sure RightValue is always properly instantiated in preheader;
Updated test;


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73496/new/

https://reviews.llvm.org/D73496

Files:
  llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
  llvm/test/Transforms/IRCE/non-loop-invariant-rhs-instr.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D73496.241461.patch
Type: text/x-patch
Size: 8984 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200130/e86a62c8/attachment.bin>


More information about the llvm-commits mailing list