[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin added a comment.

We could do that for loads. For example on Mips32r5 (where we need most instructions) for intrinsic **ldr_d** instead of:

  	lwr	$1, 16($5)
  	lwl	$1, 19($5)
  	lwr	$2, 20($5)
  	lwl	$2, 23($5)
  	fill.w	$w0, $1
  	insert.w	$w0[1], $2

We could use already available **ld.d** and then fix up **$w0[2]** and **$w0[3]** manually (when working with **MSA128WRegClass** / **v4i32**). **ld.d** has no alignment restrictions.

  	ld.d	$w0, 16($5)
  	copy_s.w	$1, $w0[0]
  	insert.w	$w0[2], $1
  	insert.w	$w0[3], $1

Optionally if we don't care what values are loaded in elements other then first we could just use **ld.d** and **ld.w** for **ldr_d** and **ldrq_w** respectively.

For stores however we cannot use **st.d** or **st.w** because we would write to memory we are not supposed to (we write to void* not necessarily v2i64 or v4i32).


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https://reviews.llvm.org/D73644