[PATCH] D73692: [PowerPC] Fix spilling of vector registers in PEI of EH aware functions

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, PowerPC.
Herald added subscribers: shchenz, jsji, kbarton, hiraditya, qcolombet.
Herald added a project: LLVM.

On little endian targets prior to Power9, we spill vector registers using a
swapping store (i.e. stdxvd2x saves the vector with the two doublewords in
big endian order regardless of endianness). This is generally not a problem
since we restore them using the corresponding swapping load (lxvd2x). However
if the restore is done by the unwinder, the vector register contains data in
the incorrect order.

This patch fixes that by using Altivec loads/stores for vector saves and
restores in PEI (which keep the order correct) under those specific conditions:

- Little endian target
- EH aware function
- Subtarget prior to Power9 (which has non-swapping loads/stores)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73692

Files:
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/test/CodeGen/PowerPC/CSR-fit.ll
  llvm/test/CodeGen/PowerPC/reg-scavenging.ll
  llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll

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