[PATCH] D72032: [llvm-exegesis] Add pfm counters for Zen2 (znver2).

[Ganesh Gopalasubramanian via Phabricator via llvm-commits]

GGanesh added inline comments.


================
Comment at: llvm/lib/Target/X86/X86PfmCounters.td:231
+  let IssueCounters = [
+    // FIXME: In the current model, all three AGUs are considered the same,
+    // but only two are supposed to be able to compute load addresses.
----------------
courbet wrote:
> GGanesh wrote:
> > Can you please help me to comprehend this better.
> > Zen2 has an AGU scheduler which services the AGU pipelines. 
> > So why are we considering only two will be able to compute load addresses?
> I'm not familiar at all with how AMD microarchitetcures work, but from https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 I understand that not all AGUs can do the same things ?
> 
> > Two AGUs can generate addresses for load operations and send them to the load queue. All three AGUs can generate addresses for store operations and send them to the store queue. 
> 
> 
Well! I think I need to get the wikichip URL edited. I will try to get that done.

Load and Store micro ops are sent to one 28-entry address generation unit (AGU) scheduler. There are 3 AGUs for all load and store address generation. 


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  https://reviews.llvm.org/D72032/new/

https://reviews.llvm.org/D72032