[PATCH] D73643: [WIP] Macro Fusion for RISC-V

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVMacroFusion.cpp:21
+
+// Fuse Idiom
+static bool isLEAPair(const MachineInstr *FirstMI,
----------------
Please, expand this comment.


================
Comment at: llvm/lib/Target/RISCV/RISCVMacroFusion.cpp:26
+      switch (SecondMI.getOpcode()) {
+        // LEA
+        case  RISCV::ADD:
----------------
Please, expand the acronym.


================
Comment at: llvm/lib/Target/RISCV/RISCVMacroFusion.cpp:45
+      switch (SecondMI.getOpcode()) {
+        case  RISCV::ADDI:
+          return true;
----------------
Please, add a comment.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:125
+  createMachineScheduler(MachineSchedContext *C) const override {
+    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
+    DAG->addMutation(createRISCVMacroFusionDAGMutation());
----------------
lenary wrote:
> Is this the default kind of machine scheduler? Does it necessarily make sense to schedule by liveness when RISC-V has so many registers?
Yes and yes.  By scheduling by liveness, the result is usually more friendly to both in and out of order µarchitectures.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73643/new/

https://reviews.llvm.org/D73643